Abstract: An example may include receiving a page code identifier, determining a priority of the page code identifier, queuing the page code identifier in a paging queue, retrieving content associated with the page code, and forwarding the content to one or more audio devices identified by the page code identifier when the page code has reached a top of the queue.

Abstract: A method and apparatus for dynamic allocation of processing resources and tasks, including multimedia tasks. Tasks are queued, available processing resources are identified, and the available processing resources are allocated among the tasks. The available processing resources are provided with functional programs corresponding to the tasks. The tasks are performed using available processing resources to produce resulting data, and the resulting data is passed to an input/output device.

Abstract: A method and apparatus for dynamic allocation of processing resources and tasks, including multimedia tasks. Tasks are queued, available processing resources are identified, and the available processing resources are allocated among the tasks. The available processing resources are provided with functional programs corresponding to the tasks. The tasks are performed using the available processing resources to produce resulting data, and the resulting data is passed to an input/output device.

Abstract: A method and apparatus for virtual address translation include processing that begins by receiving a memory access request that includes a virtual address. The processing continues by determining whether a physical address translation has been performed for the virtual address. Note that a physical address translation translates the virtual address into an address. The address either corresponds to physical address of memory or is further translated into another physical address of memory. The processing continues when the address, which resulted from the physical address translation or the another physical address translation, is stored in a translation look aside table (TLB). When the physical address translation or the another physical address translation has not been performed, the processing retrieves a physical page address based on a portion of the virtual address.

Abstract: A method and apparatus for managing cache memory is described. The invention improves the efficiency of cache usage by monitoring parameters of multiple caches, for example, empty space in each cache or the number of cache misses of each cache, and selectively assigns elements of data or results to a particular cache based on the monitored parameters. Embodiments of the invention can track absolute values of the monitored parameters or can track values of the monitored parameters of one cache relative to one or more other caches. Embodiments of the invention may be scaled to accommodate larger numbers of caches at a particular cache level and may be implemented among multiple cache levels.

Abstract: A method and apparatus for generating a specific computer hardware component exception handler and emulating memory accesses to such a hardware component include processing steps that begin by determining whether an address of a CPU instruction is within the address space of the computer hardware component. When the address is within the address space of the computer hardware component, the address and data size are saved in emulation registers. The processing then continues by entering a software exception handler to process the memory access requests directed to the computer hardware component based on the data size. The processing within the software exception handler begins by reading from a plurality of computer hardware component registers to obtain a register setting. The processing then continues by generating a specific computer hardware component function based on the register settings. The processing then continues by storing the specific computer hardware component function in cache memory.

Abstract: A method and apparatus for managing cache memory is described. The invention improves the efficiency of cache usage by monitoring parameters of multiple caches, for example, empty space in each cache or the number of cache misses of each cache, and selectively assigns elements of data or results to a particular cache based on the monitored parameters. Embodiments of the invention can track absolute values of the monitored parameters or can track values of the monitored parameters of one cache relative to one or more other caches. Embodiments of the invention may be scaled to accommodate larger numbers of caches at a particular cache level and may be implemented among multiple cache levels.

Abstract: A method and apparatus for managing cache memory is described. The invention improves the efficiency of cache usage by monitoring parameters of multiple caches, for example, empty space in each cache or the number of cache misses of each cache, and selectively assigns elements of data or results to a particular cache based on the monitored parameters. Embodiments of the invention can track absolute values of the monitored parameters or can track values of the monitored parameters of one cache relative to one or more other caches. Embodiments of the invention may be scaled to accommodate larger numbers of caches at a particular cache level and may be implemented among multiple cache levels.

Abstract: A method and apparatus includes processing for modifying memory accesses, which begins by receiving a memory transaction. The processing continues by determining whether a translation look-aside table (TLB) entry exists for the memory access transaction. If a TLB entry does not exist, one is generated. Once a TLB entry exists for the memory access transaction, a transaction tag within the TLB is interpreted to identify an exception or a memory address space from a plurality of memory address spaces. The processing continues by interpreting the TLB entry to obtain a physical address when the tag identifies the memory address space. Having obtained the physical address, the memory address transaction is processed utilizing the physical address within the corresponding memory address space.

Abstract: A method and apparatus for address paging emulation includes processing that begins by producing an extended logical address in response to a memory access request. The extended logical address includes a logical address and an address extension. The processing then continues by determining whether an entry exists for the memory access request in a translation look aside table. Such a determination is based on the logical address. When an entry does not exists for the memory access request, the process continues by providing the extended logical address to a plurality of exception handlers. The exception handlers interpret the address extension to identify one of the exception handlers to process the extended logical address. The exception handlers include a page exception handler, a non-page exception handler, a native processor exception handler, and a page directory entry exception handler.

Abstract: A method and apparatus for processing memory access requests having enhanced functionality includes processing that begins by receiving a memory access request. The process continues by determining whether the memory access request triggers an address caching process to be performed. If so, the address caching process is performed. While performing the address caching process, a determination is made as to whether the address caching processing triggers an exception process to be performed based upon a physical address derived from the address caching process. Such address space requiring further processing includes video graphics address space, restricted memory space, read-only memory space, non-cacheable data memory space, device emulation exceptions memory space, and memory exceptions. When the exception process is triggered during the address caching process, the exception process is performed and the results are cached in an address processing cache.

Abstract: A display controller in a graphics display system executes a primitive for displaying video images including multiple overlays. The primitive improves latency tolerance of the display controller and ensures seamless transitions between each frame of video images. The primitive of the present invention is executed on a display controller including a display processor. The primitive enables the display processor to process multiple control threads independently of each other. The threads execute a program to generate display signals for a frame of video image. Each of the threads executes a switch instruction when it completes processing of pixel data. The switch instruction causes the thread to determine if it is the last thread to be processed. When a thread is not the last thread, the thread is set to an inactive state. When a thread is the last thread, the primitive reactivates the multiple control threads to process pixel data for the next frame video image.

Abstract: A single dirty bit is maintained in a memory controller for each cache line of a cached memory system using a cache write-back policy. The dirty bit is set after each write access, is reset after each read access in which a cache miss occurs, and is left unchanged after all other memory accesses. The dirty bit is used to select a delay value for submitting a retry request packet after a cache miss occurred in a memory access. The delay value minimizes memory access time by allowing for a write-back operation only when necessary.