Abstract: A frequency multiplier circuit comprising a delay line receiving at one end thereof a reference clock for generating clock tap outputs from respective ones of a plurality of period matched delay elements; a clock combining circuit responsive to pairs of tap outputs for generating a rising and falling edge of an output clock pulse from respective ones of the pairs whereby the output clock period is less than the input clock period.

Abstract: A frequency multiplier circuit comprising a delay line receiving at one end thereof a reference clock for generating clock tap outputs from respective ones of a plurality of period matched delay elements; a clock combining circuit responsive to pairs of tap outputs for generating a rising and falling edge of an output clock pulse from respective ones of the pairs whereby the output clock period is less than the input clock period.

Abstract: A method of controlling an LLC resonant converter includes programming a burst stop frequency and a burst start frequency in response to a maximum switching frequency of the LLC resonant converter. The burst stop frequency and the burst start frequency are fractions of the maximum switching frequency. The LLC resonant converter is switched in response to a feedback signal to regulate an output of the LLC resonant converter. The steps of switching the LLC resonant converter in a run state in response to the feedback signal reaching a value corresponding to the programmed burst start frequency, and stopping the switching of the LLC resonant converter in a stop state in response to the feedback signal reaching a value corresponding to the programmed burst stop frequency are repeated.

Abstract: A frequency multiplier circuit comprising a delay line receiving at one end thereof a reference clock for generating clock tap outputs from respective ones of a plurality of period matched delay elements; a clock combining circuit responsive to pairs of tap outputs for generating a rising and falling edge of an output clock pulse from respective ones of the pairs whereby the output clock period is less than the input clock period.

Abstract: A controller for use in an LLC resonant converter is disclosed. An example controller is controlled by detecting a maximum frequency signal to set a maximum switching frequency of the LLC resonant converter. A burst stop frequency and a burst start frequency are programmed in response to the maximum switching frequency. The burst stop frequency and the burst start frequency are fractions of the maximum switching frequency. The LLC resonant converter is switched in response to a feedback signal to regulate an output of the LLC resonant converter. The steps of switching the LLC resonant converter in a burst mode in response to the feedback signal reaching a value corresponding to the programmed burst start frequency and of stopping the switching of the LLC resonant converter in the burst mode in response to the feedback signal reaching a value corresponding to the programmed burst stop frequency are repeated.

Abstract: A frequency multiplier circuit comprising a delay line receiving at one end thereof a reference clock for generating clock tap outputs from respective ones of a plurality of period matched delay elements; a clock combining circuit responsive to pairs of tap outputs for generating a rising and falling edge of an output clock pulse from respective ones of the pairs whereby the output clock period is less than the input clock period.

Abstract: A frequency multiplier circuit comprising a delay line receiving at one end thereof a reference clock for generating clock tap outputs from respective ones of a plurality of period matched delay elements; a clock combining circuit responsive to pairs of tap outputs for generating a rising and falling edge of an output clock pulse from respective ones of the pairs whereby the output clock period is less than the input clock period.

Abstract: A controller for use in an LLC resonant converter is disclosed. An example controller is controlled by detecting a maximum frequency signal to set a maximum switching frequency of the LLC resonant converter. A burst stop frequency and a burst start frequency are programmed in response to the maximum switching frequency. The burst stop frequency and the burst start frequency are fractions of the maximum switching frequency. The LLC resonant converter is switched in response to a feedback signal to regulate an output of the LLC resonant converter. The steps of switching the LLC resonant converter in a burst mode in response to the feedback signal reaching a value corresponding to the programmed burst start frequency and of stopping the switching of the LLC resonant converter in the burst mode in response to the feedback signal reaching a value corresponding to the programmed burst stop frequency are repeated.

Abstract: A frequency multiplier circuit comprising a delay line receiving at one end thereof a reference clock for generating clock tap outputs from respective ones of a plurality of period matched delay elements; a clock combining circuit responsive to pairs of tap outputs for generating a rising and falling edge of an output clock pulse from respective ones of the pairs whereby the output clock period is less than the input clock period.

Abstract: A frequency multiplier circuit comprising a delay line receiving at one end thereof a reference clock for generating clock tap outputs from respective ones of a plurality of period matched delay elements; a clock combining circuit responsive to pairs of tap outputs for generating a rising and falling edge of an output clock pulse from respective ones of the pairs whereby the output clock period is less than the input clock period.

Abstract: A frequency multiplier circuit comprising a delay line receiving at one end thereof a reference clock for generating clock tap outputs from respective ones of a plurality of period matched delay elements; a clock combining circuit responsive to pairs of tap outputs for generating a rising and falling edge of an output clock pulse from respective ones of the pairs whereby the output clock period is less than the input clock period.

Abstract: A frequency multiplier circuit comprising a delay line receiving at one end thereof a reference clock for generating clock tap outputs from respective ones of a plurality of period matched delay elements; a clock combining circuit responsive to pairs of tap outputs for generating a rising and falling edge of an output clock pulse from respective ones of the pairs whereby the output clock period is less than the input clock period.

Abstract: A frequency multiplier circuit comprising a delay line receiving at one end thereof a reference clock for generating clock tap outputs from respective ones of a plurality of period matched delay elements; a clock combining circuit responsive to pairs of tap outputs for generating a rising and falling edge of an output clock pulse from respective ones of the pairs whereby the output clock period is less than the input clock period.

Abstract: A cascaded charge pump based power supply for use with low voltage dynamic random access memory (DRAM) includes a charge pump and a non-overlapping clock signal generator. The charge pump circuit has two pump cascades coupled in parallel. Each pump cascade includes a plurality of pump stages connected serially between a power supply voltage and an output supply node. Adjacent stages of each cascade are clocked on opposite phases of the system clock signal. The charge pump drives an output supply node on both the rising and falling edge of the system clock signal. A non-overlapping clock signal generator for use with a charge pump has a charge sharing transistor which equalizes the non-overlapping output clock signals through charge sharing during the non-overlap period between subsequent phases of the system clock. The charge pump and capacitors are implemented using p-channel devices and the first stage of each cascade is constructed using thin-oxide devices.

Abstract: A frequency multiplier circuit comprising a delay line receiving at one end thereof a reference clock for generating clock tap outputs from respective ones of a plurality of period matched delay elements; a clock combining circuit responsive to pairs of tap outputs for generating a rising and falling edge of an output clock pulse from respective ones of the pairs whereby the output clock period is less than the input clock period.

Abstract: A frequency multiplier circuit comprising a delay line receiving at one end thereof a reference clock for generating clock tap outputs from respective ones of a plurality of period matched delay elements; a clock combining circuit responsive to pairs of tap outputs for generating a rising and falling edge of an output clock pulse from respective ones of the pairs whereby the output clock period is less than the input clock period.

Abstract: Disclosed is a charge pump based power supply for use with low voltage dynamic random access memory (DRAM) including a charge pump, and a non-overlapping clock signal generator. The charge pump comprises two pump cascades coupled in parallel. Each pump cascade includes a plurality of pump stages connected serially between a supply voltage and an output node. Adjacent stages of each cascade are clocked on opposite phases of the system clock signal. The charge pump drives an output node on the rising and falling edge of the system clock signal. A non-overlapping clock signal generator comprises a charge sharing transistor, controlled by an equalization pulse generated by the outputs of a latch, which equalizes the non-overlapping output clock signals through charge sharing during the non-overlap period between phases of the system clock. The non-overlapping clock signal generator further comprises a transmission gate included to ensure equalization of the non-overlap period.

Abstract: Method and apparatus for implementing a variable length pipeline in a packet-driven memory control system, including a command front end and one or more parallel command sequencers. The command front end decodes an external command packet into an internal command and issues it to a selected one of the command sequencers. The command has associated therewith a desired latency value. A first group of one or more memory control steps for the given command is performed by the command front end if the desired latency value is less than a threshold latency value, or by the selected command sequencer if the desired latency value is greater than or equal to the threshold latency value. The remainder of the memory control steps required for the command are performed by the selected command sequencer. If the first control steps are to be performed by the selected command sequencer, then depending on the desired latency value, the command sequencer further may insert one or more wait states before doing so.

Abstract: A contention-free transition-based signaling scheme in which a plurality of controlling units and one or more controlled units are connected to a shared bus line, which is also connected to a bus holder cell. Each of the controlling units includes an output circuit that asserts a control signal on the bus line by synchronously asserting a logic level transition on the bus line, and each of the controlled units includes an input circuit that detects assertion of the control signal by detecting that a logic level transition has occurred on the bus line. The synchronous nature of the scheme avoids the possibility of contention because all of the controlling units that intend to assert a logic level transition in a given clock cycle sampled the current logic level at the same time (within the same prior clock cycle). They therefore all agree on the current logic level and will all assert the same opposite logic level when asserting their logic level transition.

Abstract: Method and apparatus for implementing a variable length pipeline in a packet-driven memory control system, including a command front end and one or more parallel command sequencers. The command front end decodes an external command packet into an internal command and issues it to a selected one of the command sequencers. The command has associated therewith a desired latency value. A first group of one or more memory control steps for the given command is performed by the command front end if the desired latency value is less than a threshold latency value, or by the selected command sequencer if the desired latency value is greater than or equal to the threshold latency value. The remainder of the memory control steps required for the command are performed by the selected command sequencer. If the first control steps are to be performed by the selected command sequencer, then depending on the desired latency value, the command sequencer further may insert one or more wait states before doing so.