Abstract: Systems and methods to set a voltage value associated with a memory controller coupled to a memory device are disclosed. A particular method includes comparing test data of a test path to functional data of a functional path. The functional data may be generated based on device data received at a memory controller from a memory device. The test data may be affected by a voltage value applied to a resistor arrangement in electronic communication with the test path. The voltage value may be applied to the resistor arrangement based on the comparison.

Abstract: Systems and methods to set a voltage value associated with a communication bus that includes memory controller coupled to a memory device are disclosed. A particular method may include performing a first calibration operation associated with first data written from a memory controller to a memory device. A second calibration operation may be associated with second data read at the memory controller from the memory device. The operating parameter may be set based on a result of at least one of the first and the second calibration operations at the memory device or the memory controller.

Abstract: Systems and methods to set a voltage value associated with a memory controller coupled to a memory device are disclosed. A particular method includes comparing test data of a test path to functional data of a functional path. The functional data may be generated based on device data received at a memory controller from a memory device. The test data may be affected by a voltage value applied to a resistor arrangement in electronic communication with the test path. The voltage value may be applied to the resistor arrangement based on the comparison.

Abstract: Systems and methods to set a voltage value associated with a memory controller coupled to a memory device are disclosed. A particular method includes comparing test data of a test path to functional data of a functional path. The functional data may be generated based on device data received at a memory controller from a memory device. The test data may be affected by a voltage value applied to a resistor arrangement in electronic communication with the test path. The voltage value may be applied to the resistor arrangement based on the comparison.

Abstract: Systems and methods to set a voltage value associated with a memory controller coupled to a memory device are disclosed. A particular method includes comparing test data of a test path to functional data of a functional path. The functional data may be generated based on device data received at a memory controller from a memory device. The test data may be affected by a voltage value applied to a resistor arrangement in electronic communication with the test path. The voltage value may be applied to the resistor arrangement based on the comparison.

Abstract: Systems and methods to set a voltage value associated with a communication bus that includes memory controller coupled to a memory device are disclosed. A particular method may include performing a first calibration operation associated with first data written from a memory controller to a memory device. A second calibration operation may be associated with second data read at the memory controller from the memory device. The operating parameter may be set based on a result of at least one of the first and the second calibration operations at the memory device or the memory controller.

Abstract: A method and data receiver apparatus implement a high speed, such as double data rate (DDR), memory read data eye stretcher. Altering the reference level is performed to increase the size of the data eye. Knowledge of the previous data state is used to adjust the reference level for the current data being latched so that the data eye is maximized.

Abstract: A method and data receiver apparatus implement a high speed, such as double data rate (DDR), memory read data eye stretcher and a design structure on which the subject circuit resides is provided. Altering the reference level is performed to increase the size of the data eye. Knowledge of the previous data state is used to adjust the reference level for the current data being latched so that the data eye is maximized.

Abstract: A printed circuit board assembly having an edge joined first and second sub-circuit board is provided. The first sub-circuit board includes an edge with a stair-step profile interconnection wherein each of the stairs on the profile exposes an area of a signal layer. Each exposed portion of the signal layer has a plurality of signal pads thereon. The second sub-circuit board includes an edge with an inverse stair-step profile interconnection. A pad-on-pad connector is positioned in-between and electrically interconnects the respective signal layers on each sub-circuit board.

Abstract: A first method for efficient memory usage includes (1) determining whether data retrieved from a first storage device is characterized as data that is primarily read; and (2) if data retrieved from the first storage device is characterized as data that is primarily read (a) writing the retrieved data in a temporary storage device with short write latency; and (b) writing the retrieved data in a high-density memory. Numerous other aspects are provided.

Abstract: A method and apparatus implement reduced noise coupling effects on single ended clocks, and a design structure on which the subject circuit resides is provided. A clock receiver includes a clock voltage reference that is generated from received clock peaks and valleys of a received input clock signal. The received clock peaks (VT) and the received clock valleys (VB) are continuously sampled. The clock voltage reference is set, for example, equal to an average of VT and VB; or ((VT+VB)/2).

Abstract: A device to access and/or verify connections between a chip package and a printed circuit board (“PCB”), specifically within packages lacking back-side measurement access, includes a housing for insertion between the chip package and PCB. A passageway in the housing connects an entrance and an exit from the housing. The entrance is disposed on an end of the housing facing away from the chip package. The exit is disposed on a side of the housing below the chip package such that the passageway is directed at a signal path between the chip package and the PCB. A conductor disposed in the passageway is movable between a retracted position in which a contact end of the conductor is disposed within the passageway of the housing and an extended position in which the contact end of the conductor is disposed outside of the housing and in contact with the signal path.

Abstract: A method and data receiver apparatus implement a high speed, such as double data rate (DDR), memory read data eye stretcher. Altering the reference level is performed to increase the size of the data eye. Knowledge of the previous data state is used to adjust the reference level for the current data being latched so that the data eye is maximized.

Abstract: A method and data receiver apparatus implement a high speed, such as double data rate (DDR), memory read data eye stretcher and a design structure on which the subject circuit resides is provided. Altering the reference level is performed to increase the size of the data eye. Knowledge of the previous data state is used to adjust the reference level for the current data being latched so that the data eye is maximized.

Abstract: A memory arrangement, where a memory control logic, which drives a memory array, is maintained in a volatile power domain, and clock redrive circuitry, address control redrive circuitry, data transceiver, and the memory array itself are all maintained in a non-volatile power domain, in order to increase the effective life time of a battery backup system. The memory arrangement includes buffering circuitry to prevent leakage currents, and the appropriate control of nets between the memory control logic and the memory array, in order to avoid additional sources of leakage current and bus driver contentions.