Patents by Inventor Paul Wai Kie Poon

Paul Wai Kie Poon has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8987119
    Abstract: A method of making a semiconductor device includes providing an insulating layer containing a plurality of openings, forming a first semiconductor layer in the plurality of openings in the insulating layer and over the insulating layer, and removing a first portion of the first semiconductor layer, such that first conductivity type second portions of the first semiconductor layer remain in lower portions of the plurality of openings in the insulating layer, and upper portions of the plurality of openings in the insulating layer remain unfilled. The method also includes forming a second semiconductor layer in the upper portions of the plurality of openings in the insulating layer and over the insulating layer, and removing a first portion of the second semiconductor layer located over the insulating layer.
    Type: Grant
    Filed: February 14, 2011
    Date of Patent: March 24, 2015
    Assignee: Sandisk 3D LLC
    Inventors: Vance Dunton, S. Brad Herner, Paul Wai Kie Poon, Chuanbin Pan, Michael Chan, Michael Konevecki, Usha Raghuram
  • Patent number: 8329512
    Abstract: A method of making a device includes forming a first photoresist layer over a sacrificial layer, patterning the first photoresist layer to form first photoresist features, rendering the first photoresist features insoluble to a solvent, forming a second photoresist layer over the first photoresist features, patterning the second photoresist layer to form second photoresist features, forming a spacer layer over the first and second photoresist features, etching the spacer layer to form spacer features and to expose the first and second photoresist features, forming third photoresist features between the spacer features, removing the spacer features, and patterning the sacrificial layer using the first, second and third photoresist features as a mask to form sacrificial features.
    Type: Grant
    Filed: May 3, 2012
    Date of Patent: December 11, 2012
    Assignee: SanDisk 3D LLC
    Inventors: Natalie Nguyen, Paul Wai Kie Poon, Steven J. Radigan, Michael Konevecki, Yung-Tin Chen, Raghuveer Makala, Vance Dunton
  • Publication number: 20120276744
    Abstract: A method of making a device includes forming a first photoresist layer over a sacrificial layer, patterning the first photoresist layer to form first photoresist features, rendering the first photoresist features insoluble to a solvent, forming a second photoresist layer over the first photoresist features, patterning the second photoresist layer to form second photoresist features, forming a spacer layer over the first and second photoresist features, etching the spacer layer to form spacer features and to expose the first and second photoresist features, forming third photoresist features between the spacer features, removing the spacer features, and patterning the sacrificial layer using the first, second and third photoresist features as a mask to form sacrificial features.
    Type: Application
    Filed: May 3, 2012
    Publication date: November 1, 2012
    Applicant: SanDisk 3D LLC
    Inventors: Natalie Nguyen, Paul Wai Kie Poon, Steven J. Radigan, Michael Konevecki, Yung-Tin Chen, Raghuveer Makala, Vance Dunton
  • Patent number: 8241969
    Abstract: A method of making a device includes forming a first photoresist layer over a sacrificial layer, patterning the first photoresist layer to form first photoresist features, rendering the first photoresist features insoluble to a solvent, forming a second photoresist layer over the first photoresist features, patterning the second photoresist layer to form second photoresist features, forming a spacer layer over the first and second photoresist features, etching the spacer layer to form spacer features and to expose the first and second photoresist features, forming third photoresist features between the spacer features, removing the spacer features, and patterning the sacrificial layer using the first, second and third photoresist features as a mask to form sacrificial features.
    Type: Grant
    Filed: August 24, 2011
    Date of Patent: August 14, 2012
    Assignee: SanDisk 3D LLC
    Inventors: Natalie Nguyen, Paul Wai Kie Poon, Steven J. Radigan, Michael Konevecki, Yung-Tin Chen, Raghuveer Makala, Vance Dunton
  • Patent number: 8187932
    Abstract: A non-volatile memory device contains a three dimensional stack of horizontal diodes located in a trench in an insulating material, a plurality of storage elements, a plurality of word lines extending substantially vertically, and a plurality of bit lines. Each of the plurality of bit lines has a first portion that extends up along at least one side of the trench and a second portion that extends substantially horizontally through the three dimensional stack of the horizontal diodes. Each of the horizontal diodes is a steering element of a respective non-volatile memory cell of the non-volatile memory device, and each of the plurality of storage elements is located adjacent to a respective steering element.
    Type: Grant
    Filed: October 15, 2010
    Date of Patent: May 29, 2012
    Assignee: SanDisk 3D LLC
    Inventors: Natalie Nguyen, Paul Wai Kie Poon, Steven J. Radigan, Michael Konevecki, Raghuveer S. Makala
  • Publication number: 20120091413
    Abstract: A non-volatile memory device contains a three dimensional stack of horizontal diodes located in a trench in an insulating material, a plurality of storage elements, a plurality of word lines extending substantially vertically, and a plurality of bit lines. Each of the plurality of bit lines has a first portion that extends up along at least one side of the trench and a second portion that extends substantially horizontally through the three dimensional stack of the horizontal diodes. Each of the horizontal diodes is a steering element of a respective non-volatile memory cell of the non-volatile memory device, and each of the plurality of storage elements is located adjacent to a respective steering element.
    Type: Application
    Filed: October 15, 2010
    Publication date: April 19, 2012
    Applicant: SanDisk 3D LLC
    Inventors: Natalie Nguyen, Paul Wai Kie Poon, Steven J. Radigan, Michael Konevecki, Raghuveer S. Makala
  • Publication number: 20120049186
    Abstract: Test structures are formed during semiconductor processing with a single mask that is used in a manner that also allows alignment marks to be formed which do not interfere with one another as subsequent layers are patterned. The test structures can provide insight into performance characteristics of different types of devices as the semiconductor process proceeds.
    Type: Application
    Filed: August 31, 2010
    Publication date: March 1, 2012
    Inventors: Calvin K. Li, Yung-Tin Chen, En-Hsing Chen, Paul Wai Kie Poon
  • Publication number: 20110306174
    Abstract: A method of making a device includes forming a first photoresist layer over a sacrificial layer, patterning the first photoresist layer to form first photoresist features, rendering the first photoresist features insoluble to a solvent, forming a second photoresist layer over the first photoresist features, patterning the second photoresist layer to form second photoresist features, forming a spacer layer over the first and second photoresist features, etching the spacer layer to form spacer features and to expose the first and second photoresist features, forming third photoresist features between the spacer features, removing the spacer features, and patterning the sacrificial layer using the first, second and third photoresist features as a mask to form sacrificial features.
    Type: Application
    Filed: August 24, 2011
    Publication date: December 15, 2011
    Inventors: Natalie Nguyen, Paul Wai Kie Poon, Steven J. Radigan, Michael Konevecki, Yung-Tin Chen, Raghuveer Makala, Vance Dunton
  • Patent number: 8076056
    Abstract: A method of making a device includes forming an underlying mask layer over an underlying layer, forming a first mask layer over the underlying mask layer, patterning the first mask layer to form first mask features, undercutting the underlying mask layer to form underlying mask features using the first mask features as a mask, removing the first mask features, and patterning the underlying layer using at least the underlying mask features as a mask.
    Type: Grant
    Filed: October 6, 2008
    Date of Patent: December 13, 2011
    Assignee: SanDisk 3D LLC
    Inventors: Chun-Ming Wang, Steven Maxwell, Paul Wai Kie Poon, Yung-Tin Chen
  • Patent number: 8026178
    Abstract: A method of making a device includes forming a first photoresist layer over a sacrificial layer, patterning the first photoresist layer to form first photoresist features, rendering the first photoresist features insoluble to a solvent, forming a second photoresist layer over the first photoresist features, patterning the second photoresist layer to form second photoresist features, forming a spacer layer over the first and second photoresist features, etching the spacer layer to form spacer features and to expose the first and second photoresist features, forming third photoresist features between the spacer features, removing the spacer features, and patterning the sacrificial layer using the first, second and third photoresist features as a mask to form sacrificial features.
    Type: Grant
    Filed: January 12, 2010
    Date of Patent: September 27, 2011
    Assignee: SanDisk 3D LLC
    Inventors: Natalie Nguyen, Paul Wai Kie Poon, Steven J. Radigan, Michael Konevecki, Yung-Tin Chen, Raghuveer Makala, Vance Dunton
  • Patent number: 7998640
    Abstract: A mask is reused to form the same pattern in multiple layers in semiconductor processing. Reference marks that allow alignment accuracy to be checked are also formed with the mask. The manner of using the mask advantageously mitigates interference between reference marks in different layers.
    Type: Grant
    Filed: June 30, 2007
    Date of Patent: August 16, 2011
    Assignee: SanDisk Corporation
    Inventors: Calvin K. Li, Yung-Tin Chen, En-Hsing Chen, Paul Wai Kie Poon
  • Publication number: 20110171815
    Abstract: A method of making a device includes forming a first photoresist layer over a sacrificial layer, patterning the first photoresist layer to form first photoresist features, rendering the first photoresist features insoluble to a solvent, forming a second photoresist layer over the first photoresist features, patterning the second photoresist layer to form second photoresist features, forming a spacer layer over the first and second photoresist features, etching the spacer layer to form spacer features and to expose the first and second photoresist features, forming third photoresist features between the spacer features, removing the spacer features, and patterning the sacrificial layer using the first, second and third photoresist features as a mask to form sacrificial features.
    Type: Application
    Filed: January 12, 2010
    Publication date: July 14, 2011
    Inventors: Natalie NGUYEN, Paul Wai Kie Poon, Steven J. Radigan, Michael Konevecki, Yung-Tin Chen, Raghuveer Makala, Vance Dunton
  • Publication number: 20110136326
    Abstract: A method of making a semiconductor device includes providing an insulating layer containing a plurality of openings, forming a first semiconductor layer in the plurality of openings in the insulating layer and over the insulating layer, and removing a first portion of the first semiconductor layer, such that first conductivity type second portions of the first semiconductor layer remain in lower portions of the plurality of openings in the insulating layer, and upper portions of the plurality of openings in the insulating layer remain unfilled. The method also includes forming a second semiconductor layer in the upper portions of the plurality of openings in the insulating layer and over the insulating layer, and removing a first portion of the second semiconductor layer located over the insulating layer.
    Type: Application
    Filed: February 14, 2011
    Publication date: June 9, 2011
    Applicant: SanDisk 3D LLC
    Inventors: Vance DUNTON, S. Brad Herner, Paul Wai Kie Poon, Chuanbin Pan, Michael Chan, Michael Konevecki, Usha Raghuram
  • Patent number: 7932157
    Abstract: Test structures are formed during semiconductor processing. The test structures allow performance characteristics to be monitored as the process proceeds. The test structures are formed with a single mask that is used in a manner that also allows alignment marks to be formed which do not interfere with one another as subsequent levels are patterned. The manner of using the mask also allows different types of test structures having different features to be formed. The different types of test structures can provide insight into performance characteristics of different types of devices.
    Type: Grant
    Filed: June 30, 2007
    Date of Patent: April 26, 2011
    Assignee: SanDisk Corporation
    Inventors: Calvin K. Li, Yung-Tin Chen, En-Hsing Chen, Paul Wai Kie Poon
  • Patent number: 7923305
    Abstract: A method of making a device includes forming a first sacrificial layer over an underlying layer, forming a first photoresist layer over the first sacrificial layer, patterning the first photoresist layer to form first photoresist features, rendering the first photoresist features insoluble to a solvent, forming a second photoresist layer over the first photoresist features, patterning the second photoresist layer to form second photoresist features, etching the first sacrificial layer using both the first and the second photoresist features as a mask to form first sacrificial features, forming a spacer layer over the first sacrificial features, etching the spacer layer to form spacer features and to expose the sacrificial features, removing the first sacrificial features, and etching at least part of the underlying layer using the spacer features as a mask.
    Type: Grant
    Filed: January 12, 2010
    Date of Patent: April 12, 2011
    Assignee: SanDisk 3D LLC
    Inventors: Natalie Nguyen, Paul Wai Kie Poon, Steven J. Radigan, Michael Konevecki, Yung-Tin Chen
  • Patent number: 7906392
    Abstract: A method of making a semiconductor device includes providing an insulating layer containing a plurality of openings, forming a first semiconductor layer in the plurality of openings in the insulating layer and over the insulating layer, and removing a first portion of the first semiconductor layer, such that first conductivity type second portions of the first semiconductor layer remain in lower portions of the plurality of openings in the insulating layer, and upper portions of the plurality of openings in the insulating layer remain unfilled. The method also includes forming a second semiconductor layer in the upper portions of the plurality of openings in the insulating layer and over the insulating layer, and removing a first portion of the second semiconductor layer located over the insulating layer.
    Type: Grant
    Filed: January 15, 2008
    Date of Patent: March 15, 2011
    Assignee: SanDisk 3D LLC
    Inventors: Vance Dunton, S. Brad Herner, Paul Wai Kie Poon, Chuanbin Pan, Michael Chan, Michael Konevecki, Usha Raghuram
  • Patent number: 7830028
    Abstract: Different types of test structures are formed during semiconductor processing. One type of test structure comprises features that are aligned with one another and that are formed from different layers. Other types of test structures comprise features formed from respective layers that are not aligned with other test structure features. The different types of test structures are formed with a single mask that is used in a manner that also allows alignment marks to be formed which do not interfere with one another as subsequent layers are patterned. The different types of test structures can provide insight into performance characteristics of different types of devices as the semiconductor process proceeds.
    Type: Grant
    Filed: June 30, 2007
    Date of Patent: November 9, 2010
    Assignee: SanDisk Corporation
    Inventors: Calvin K. Li, Yung-Tin Chen, En-Hsing Chen, Paul Wai Kie Poon
  • Publication number: 20100086875
    Abstract: A method of making a device includes forming an underlying mask layer over an underlying layer, forming a first mask layer over the underlying mask layer, patterning the first mask layer to form first mask features, undercutting the underlying mask layer to form underlying mask features using the first mask features as a mask, removing the first mask features, and patterning the underlying layer using at least the underlying mask features as a mask.
    Type: Application
    Filed: October 6, 2008
    Publication date: April 8, 2010
    Inventors: Chung-Ming Wang, Steven Maxwell, Paul Wai Kie Poon, Yung-Tin Chen
  • Publication number: 20090179310
    Abstract: A method of making a semiconductor device includes providing an insulating layer containing a plurality of openings, forming a first semiconductor layer in the plurality of openings in the insulating layer and over the insulating layer, and removing a first portion of the first semiconductor layer, such that first conductivity type second portions of the first semiconductor layer remain in lower portions of the plurality of openings in the insulating layer, and upper portions of the plurality of openings in the insulating layer remain unfilled. The method also includes forming a second semiconductor layer in the upper portions of the plurality of openings in the insulating layer and over the insulating layer, and removing a first portion of the second semiconductor layer located over the insulating layer.
    Type: Application
    Filed: January 15, 2008
    Publication date: July 16, 2009
    Inventors: Vance Dunton, S. Brad Herner, Paul Wai Kie Poon, Chuanbin Pan, Michael Chan, Michael Konevecki, Usha Raghuram
  • Publication number: 20090004879
    Abstract: Test structures are formed during semiconductor processing. The test structures allow performance characteristics to be monitored as the process proceeds. The test structures are formed with a single mask that is used in a manner that also allows alignment marks to be formed which do not interfere with one another as subsequent levels are patterned. The manner of using the mask also allows different types of test structures having different features to be formed. The different types of test structures can provide insight into performance characteristics of different types of devices.
    Type: Application
    Filed: June 30, 2007
    Publication date: January 1, 2009
    Inventors: Calvin K. Li, Yung-Tin Chen, En-Hsing Chen, Paul Wai Kie Poon