Patents by Inventor Paul Wallner
Paul Wallner has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10127176Abstract: In accordance with an embodiment, a receiver includes a receiving unit configured to receive a first received bus signal and a second received bus signal based on a bus input signal. The receiver also includes a first state machine configured to determine that a first output signal is a first symbol in response to the first received bus signal transitioning from a first bus state to a second bus state and staying in the second bus state for less than a first predetermined period of time, and a second symbol in response to the first received bus signal transitioning from the first bus state to the second bus state and staying in the second bus state for at least the first predetermined period of time. Additionally, the receiver includes a second state machine.Type: GrantFiled: January 31, 2017Date of Patent: November 13, 2018Assignee: INFINEON TECHNOLOGIES AGInventors: Paul Wallner, Dieter Metzner, Martin Streibl
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Publication number: 20170139870Abstract: In accordance with an embodiment, a receiver includes a receiving unit configured to receive a first received bus signal and a second received bus signal based on a bus input signal. The receiver also includes a first state machine configured to determine that a first output signal is a first symbol in response to the first received bus signal transitioning from a first bus state to a second bus state and staying in the second bus state for less than a first predetermined period of time, and a second symbol in response to the first received bus signal transitioning from the first bus state to the second bus state and staying in the second bus state for at least the first predetermined period of time. Additionally, the receiver includes a second state machine.Type: ApplicationFiled: January 31, 2017Publication date: May 18, 2017Inventors: Paul Wallner, Dieter Metzner, Martin Streibl
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Patent number: 9582451Abstract: In accordance with an embodiment, a receiver includes a first state machine configured to be coupled to a bus. The first state machine is configured to determine that a first output signal is a first symbol if a first received bus signal transitions from a first bus state to a second bus state and stays in the second bus state for less than a first predetermined period of time, and the first output signal is a second symbol if the first received bus signal transitions from the first bus state to the second bus state and stays in the second bus state for at least the first predetermined period of time.Type: GrantFiled: February 1, 2013Date of Patent: February 28, 2017Assignee: Infineon Technologies AGInventors: Paul Wallner, Dieter Metzner, Martin Streibl
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Patent number: 9417983Abstract: An electrical circuit for driving a bus is described that includes at least one branch coupled to at least one signal line at a termination of the bus and a transmit data input configured to receive data that the electrical circuit drives across the bus. The electrical circuit also includes a current detection unit coupled to the at least one branch, which is configured to detect a current through the at least one branch. The electrical circuit also includes an over-current determination unit coupled to both the current detection unit and the transmit data input. The over-current determination unit is configured to determine an over-current condition at the at least one branch based on the current at the at least one branch and the data at the transmit data input.Type: GrantFiled: June 3, 2013Date of Patent: August 16, 2016Assignee: Infineon Technologies AGInventors: Dieter Metzner, Peter Widerin, Paul Wallner, Thomas Rickes
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Patent number: 9172235Abstract: An electrical circuit for driving a bus is described that includes a plurality of branches coupled to at least one signal line at a termination of the bus and a transmit data input configured to receive data that the electrical circuit drives across the bus. The electrical circuit also includes an over-current validation unit coupled to the transmit data input which is configured to validate an over-current condition detected at a first branch of the plurality of branches based at least in part on the data at the transmit data input. The electrical circuit also includes a branch control unit coupled to the over-current validation unit which is configured to disable at least one of the plurality of branches in response to a validated over-current condition at the first branch.Type: GrantFiled: June 3, 2013Date of Patent: October 27, 2015Assignee: Infineon Technologies AGInventors: Dieter Metzner, Peter Widerin, Paul Wallner, Thomas Rickes
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Publication number: 20140355158Abstract: An electrical circuit for driving a bus is described that includes a plurality of branches coupled to at least one signal line at a termination of the bus and a transmit data input configured to receive data that the electrical circuit drives across the bus. The electrical circuit also includes an over-current validation unit coupled to the transmit data input which is configured to validate an over-current condition detected at a first branch of the plurality of branches based at least in part on the data at the transmit data input. The electrical circuit also includes a branch control unit coupled to the over-current validation unit which is configured to disable at least one of the plurality of branches in response to a validated over-current condition at the first branch.Type: ApplicationFiled: June 3, 2013Publication date: December 4, 2014Inventors: Dieter Metzner, Peter Widerin, Paul Wallner, Thomas Rickes
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Publication number: 20140359190Abstract: An electrical circuit for driving a bus is described that includes at least one branch coupled to at least one signal line at a termination of the bus and a transmit data input configured to receive data that the electrical circuit drives across the bus. The electrical circuit also includes a current detection unit coupled to the at least one branch, which is configured to detect a current through the at least one branch. The electrical circuit also includes an over-current determination unit coupled to both the current detection unit and the transmit data input. The over-current determination unit is configured to determine an over-current condition at the at least one branch based on the current at the at least one branch and the data at the transmit data input.Type: ApplicationFiled: June 3, 2013Publication date: December 4, 2014Inventors: Dieter Metzner, Peter Widerin, Paul Wallner, Thomas Rickes
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Publication number: 20140245711Abstract: An expanded metal is provided including a plurality of integral strands defining diamond shapes, each diamond shape having a long dimension as measured from two opposing vertices and a short dimension, generally transverse to the long direction, as measured between two other opposing vertices, such that the long dimension is less than twice the short dimension.Type: ApplicationFiled: February 24, 2014Publication date: September 4, 2014Applicant: WALLNER TOOLING\EXPAC, INC.Inventors: MICHAEL H. WALLNER, PAUL WALLNER
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Publication number: 20140223050Abstract: In accordance with an embodiment, a receiver includes a first state machine configured to be coupled to a bus. The first state machine is configured to determine that a first output signal is a first symbol if a first received bus signal transitions from a first bus state to a second bus state and stays in the second bus state for less than a first predetermined period of time, and the first output signal is a second symbol if the first received bus signal transitions from the first bus state to the second bus state and stays in the second bus state for at least the first predetermined period of time.Type: ApplicationFiled: February 1, 2013Publication date: August 7, 2014Applicant: INFINEON TECHNOLOGIES AGInventors: Paul Wallner, Dieter Metzner, Martin Streibl
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Patent number: 8696781Abstract: An expanded metal is provided including a plurality of integral strands defining diamond shapes, each diamond shape having a long dimension as measured from two opposing vertices and a short dimension, generally transverse to the long direction, as measured between two other opposing vertices, such that the long dimension is less than twice the short dimension.Type: GrantFiled: September 27, 2010Date of Patent: April 15, 2014Assignee: Wallner Tooling\Expac, Inc.Inventors: Michael H. Wallner, Paul Wallner
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Publication number: 20130333172Abstract: An expanded metal is provided including a plurality of integral strands defining diamond shapes, each diamond shape having a long dimension as measured from two opposing vertices and a short dimension, generally transverse to the long direction, as measured between two other opposing vertices, such that the long dimension is less than twice the short dimension.Type: ApplicationFiled: August 19, 2013Publication date: December 19, 2013Applicant: WALLNER TOOLING\EXPAC, INC.Inventors: MICHAEL H. WALLNER, PAUL WALLNER
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Publication number: 20120144792Abstract: An expanded metal is provided including a plurality of integral strands defining diamond shapes, each diamond shape having a long dimension as measured from two opposing vertices and a short dimension, generally transverse to the long direction, as measured between two other opposing vertices, such that the long dimension is less than twice the short dimension.Type: ApplicationFiled: September 27, 2010Publication date: June 14, 2012Applicant: WALLNER TOOLING\EXPAC, INC.Inventors: MICHAEL WALLNER, PAUL WALLNER
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Patent number: 8108643Abstract: In a semiconductor memory system having a loop forward architecture, the command, address and write data stream and the separate read data stream in form of protocol-based frames transmitted to/from memory chips in the following order: memory controller to the first memory chip, to the second memory chip, to the third memory chip and to the fourth memory chip and the read data stream is transferred from the fourth memory chip to the memory controller. With each command usually one of four memory chips is accessed for data processing, while three of four memory chips have only to fulfil a simple re-drive of CAwD stream and read data stream. By separately transferring a rank select signal not embedded in the frame from the memory controller to each memory chip a lot of more flexibility for these tasks can be achieved.Type: GrantFiled: July 29, 2005Date of Patent: January 31, 2012Assignee: Qimonda AGInventors: Paul Wallner, Peter Gregorius
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Publication number: 20110067372Abstract: An expanded metal is provided including a plurality of integral strands defining diamond shapes, each diamond shape having a long dimension as measured from two opposing vertices and a short dimension, generally transverse to the long direction, as measured between two other opposing vertices, such that the long dimension is less than twice the short dimension.Type: ApplicationFiled: September 27, 2010Publication date: March 24, 2011Inventors: Michael H. Wallner, Paul Wallner
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Patent number: 7733732Abstract: A method of refreshing the content of a memory cell of a memory arrangement includes selectively controlling a refreshing device of the memory arrangement via an interface of the memory arrangement or by an internal control device of the memory arrangement to refresh the content of the memory arrangement.Type: GrantFiled: September 17, 2007Date of Patent: June 8, 2010Assignee: Qimonda AGInventors: Christian Sichert, Paul Wallner
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Patent number: 7725647Abstract: A memory arrangement includes an interface configured to transmit data in the form of data packets according to a predefined protocol. The memory arrangement includes at least two memory banks. Each memory bank includes at least one memory cell. The memory arrangement includes at least two memory bank access devices configured to facilitate accessing the data of the at least one memory cell of each of the at least two memory banks. The memory arrangement includes at least two data packet processing devices configured to encode and/or decode the data packets. The at least two data packet processing devices are assigned to different memory bank access devices.Type: GrantFiled: February 27, 2007Date of Patent: May 25, 2010Assignee: Qimonda AGInventors: Paul Wallner, Tim Schoenauer, Peter Gregorius, Daniel Kehrer
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Patent number: 7663964Abstract: A memory device including a memory cell array; an input circuit providing drive signals to the memory cell array dependent on externally received command data; an output buffer buffering data read out from the memory cell array; and a timer driving the output buffer such that the buffered data are provided at an output after an adjustable time interval has elapsed, the adjustable time interval beginning with the provision of the drive signals.Type: GrantFiled: April 16, 2007Date of Patent: February 16, 2010Assignee: Qimonda AGInventors: Paul Wallner, Peter Gregorius
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Patent number: 7633814Abstract: A memory device comprising a memory cell array; an input circuit for receiving command data and providing drive signals to the memory cell array; an output buffer for buffering data read out from the memory cell array; and a timer for driving the output buffer such that the buffered data are provided at an output after a predetermined time interval has elapsed, the predetermined time interval beginning with the provision of the drive signals.Type: GrantFiled: April 16, 2007Date of Patent: December 15, 2009Assignee: Qimonda AGInventors: Paul Wallner, Stefan Dietrich, Peter Gregorius
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Patent number: 7587655Abstract: Method and apparatus for communication (e.g., transmitting and/or receiving) command, address and data signals from a memory device to a memory controller or vice versa. The data signals are transferred with a first rate and command signals and/or address signals are transferred with a second rate lower than a first rate. Additionally or alternatively a command sequence code identifying a command sequence from a predefined group of command sequences is transferred with the first or with the second rate.Type: GrantFiled: October 26, 2005Date of Patent: September 8, 2009Assignee: Infineon Technologies AGInventors: Paul Wallner, Andre Schaefer, Thomas Hein, Peter Gregorius
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Patent number: 7536528Abstract: A memory arrangement includes an interface configured to transmit, code and/or decode data in the form of data packets in accordance with a predefined protocol. The memory arrangement includes at least two memory banks, each memory bank including at least one memory cell. The memory arrangement includes at least two memory-bank access devices configured to facilitate accessing the data of the at least one memory cell of each of the at least two memory banks. The memory arrangement includes at least two temporary storage devices configured to temporarily store data being transmitted between the interface and the at least two memory-bank access devices. Each of the at least two temporary storage devices is connected to the interface and to one of the at least two memory-bank access devices.Type: GrantFiled: February 27, 2007Date of Patent: May 19, 2009Assignee: Qimonda AGInventors: Paul Wallner, Chaitanya Dudha