Abstract: A method of decoding a digitally encoded signal having plural channels includes sampling a transient portion of a master filter mask, storing matched filter coefficients obtained from the sampling, receiving the digitally encoded signal, channelizing the digitally encoded signal into the plural channels, and generating a channel matched filter mask for each one of the plural channels using a subset of the stored coefficients. The method also includes filtering each one of the plural channels, in the frequency domain, based on the channel matched filter mask generated for each of the plural channels. Also disclosed are related methods using a burst reconstruction buffer, per channel distortion equalization, channel estimation and activity monitoring, and noise floor estimation, as well as corresponding apparatuses.

Abstract: A apparatus (700) and method (600) are presented for preventing glitches and data loss in an Digital Base Band (DBB) portion (110) of an Ultra Wideband (UWB) receiver. a first and a second recovered clock (111, 112) and an external clock (109) can be input to a switch (116). Logical rules (490) can be used to determine conditions under which to hold the state of an output clock (310, 320) based on the states of a first clock (410, 420, 430, 440) and a second clock (450, 460, 470, 480) and the state of a switch request signal (312). In addition to holding the state of the output clock, a first data stream (501) associated with the first clock and a second data stream (502) associated with the second clock can be synchronized such that when switching from the first to the second clock no data loss will be experienced in the data stream.

Abstract: A circuit (500) and method (600, 700) are presented for detecting non-volatile memory (NVM) devices (321, 323, 325) associated with computing device during a processor boot sequence. The NVM devices have corresponding starting addresses (331, 332, 333)and the processor begins operation from a first starting address associated with a first NVM devices after a reset interval. The circuit includes NVM device detectors which determine whether the NVM devices are present by reading (512, 514, 516) an authentication code including an identifier, a codeword, a NVM size, or a NVM type from a predetermined location within the each of the NVM devices if present. If the NVM device is not present, the detector returns an instruction (513, 515, 517) for the processor to continue execution at a starting addresses for a next NVM device.