Patents by Inventor Paul-Werner Von Basse
Paul-Werner Von Basse has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7239729Abstract: A circuit and method are provided for ensuring that a fingerprint sensor is started automatically when a finger is rested thereon such that a sufficiently contrasting image can be produced. A difference between a maximum and a minimum value of the sensor signals is generated wherein, if the difference is sufficiently large, indicating a sufficient contrast of an image to be produced, a normal scanning operation of the fingerprint sensor is initiated, thus ensuring that the complete fingerprint image is produced, a normal scanning operation of the fingerprint sensor is initiated, thus ensuring that the complete fingerprint images produced are of satisfactory quality.Type: GrantFiled: February 7, 2001Date of Patent: July 3, 2007Assignee: Siemens AktiengesellschaftInventors: Stephan Marksteiner, Paul-Werner von Basse
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Patent number: 7054469Abstract: A conductor layer is patterned into flat portions, for example of a fingerprint sensor that effects capacitive measurement. The conductor layer is fragmented in a lattice-like manner by cutouts so that an applied passivation layer rests on a base layer that is present beneath the conductor layer. The interlaminar shear strength of the passivation is increased in this way.Type: GrantFiled: January 30, 2002Date of Patent: May 30, 2006Assignee: Infineon Technologies AGInventors: Siegfried Röhl, Paul-Werner Von Basse, Thomas Scheiter, Thorsten Sasse, Heinz Opolka
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Patent number: 6714392Abstract: An electronic component is described and has a dielectric layer which is constructed on a substrate, conductive surfaces that are constructed on the dielectric layer, and an electrically conductive guard structure. The guard structure is disposed in a plane above the conductive surfaces such that the conductive surfaces are not completely covered by the guard structure.Type: GrantFiled: July 16, 2001Date of Patent: March 30, 2004Assignee: Infineon Technologies AGInventors: Heinz Opolka, Paul-Werner Von Basse, Thomas Scheiter, Rainer Grossmann, Christian Peters, Reinhard Fischbach, Andreas Gaymann, Thomas Rosteck, Domagoj Siprak, Thorsten Sasse, Reinhard Göllner, Justin Bierner, Michael Melzl, Klaus Hammer, Markus Witte
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Patent number: 6664612Abstract: A semiconductor component with passivation includes at least two double passivating layers, of which an uppermost is applied to a planar surface of a layer located therebelow. The double passivating layers include two layers of different dielectric materials, for example silicon oxide and silicon nitride. The respective thicknesses of the individual passivating layers can be adapted to dimensions of the structuring of the layer to which the passivation is applied. This produces a reliable passivation which is particularly suitable for capacitively measuring fingerprint sensors.Type: GrantFiled: January 9, 2001Date of Patent: December 16, 2003Assignee: Infineon Technologies AGInventors: Josef Willer, Paul-Werner Von Basse, Thomas Scheiter
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Patent number: 6583632Abstract: A grid of capacitor surfaces is connected to read lines and control lines. The read lines are connected alternately to the output of a feedback operational amplifier and to a collecting capacitor. The capacitances to be measured are charged repeatedly and the charges are collected on the collecting capacitors. Between the charging operations, the potential on the read lines is kept constant through the use of the low-resistance output of the operational amplifier. The use of this method in the case of a fingerprint sensor makes it possible to evaluate all the read lines together.Type: GrantFiled: January 23, 2001Date of Patent: June 24, 2003Assignee: Micronas GmbHInventors: Paul-Werner Von Basse, Josef Willer
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Publication number: 20030002721Abstract: The circuit arrangement or the operating method ensure that the fingerprint sensor is started automatically when a sufficiently high-contrast image can be produced. To this end, test runs are carried out in which only pan of the pixels, for instance along a column or line of a matrix-like array in a square raster, are taken into account. It is determined whether the difference between the maximum and minimum values of the sensor signals exceeds a predetermined value. In said case, the normal scanning procedure of the fingerprint sensor is started.Type: ApplicationFiled: August 6, 2002Publication date: January 2, 2003Inventors: Stephan Marksteiner, Paul-Werner Von Basse
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Patent number: 6445046Abstract: A number of memory cell lines insulated from one another and that respectively comprise a first doped region and a second doped region between which a gate dielectric, which contains a material with charge carrier traps and a number of gate electrodes. The spacing of neighboring gate electrodes is smaller than the dimensions of the gate electrodes. The information is stored by introduction of charge carriers into the gate dielectric. The gate electrodes are preferably manufactured with the assistance of a spacer technique.Type: GrantFiled: June 15, 1999Date of Patent: September 3, 2002Assignee: Siemens AktiengesellschaftInventors: Franz Hofmann, Josef Willer, Hans Reisinger, Paul Werner von Basse, Wolfgang Krautschneider
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Publication number: 20020109209Abstract: A conductor layer is patterned into flat portions, for example of a fingerprint sensor that effects capacitive measurement. The conductor layer is fragmented in a lattice-like manner by cutouts so that an applied passivation layer rests on a base layer that is present beneath the conductor layer. The interlaminar shear strength of the passivation is increased in this way.Type: ApplicationFiled: January 30, 2002Publication date: August 15, 2002Inventors: Siegfried Rohl, Paul-Werner Von Basse, Thomas Scheiter, Thorsten Sasse, Heinz Opolka
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Publication number: 20020066942Abstract: An electronic component is described and has a dielectric layer which is constructed on a substrate, conductive surfaces that are constructed on the dielectric layer, and an electrically conductive guard structure. The guard structure is disposed in a plane above the conductive surfaces such that the conductive surfaces are not completely covered by the guard structure.Type: ApplicationFiled: July 16, 2001Publication date: June 6, 2002Inventors: Heinz Opolka, Paul-Werner Von Basse, Thomas Scheiter, Rainer Grossmann, Christian Peters, Reinhard Fischbach, Andreas Gaymann, Thomas Rosteck, Domagoj Siprak, Thorsten Sasse, Reinhard Gollner, Justin Bierner, Michael Melzl, Klaus Hammer, Markus Witte
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Patent number: 6365888Abstract: A grid-shaped array of conductor areas is used for capacitive image acquisition. Shielding conductors are disposed in each case between the conductors that are provided for measurement. During a plurality of charging and discharging cycles, the potential is always carried along on the conductors belonging to a respective pixel in order to prevent displacement currents between the shielding capacitors. By way of example, a compensation line with a feedback operational amplifier can be used for identically altering the electrical potentials on the conductors.Type: GrantFiled: February 13, 2001Date of Patent: April 2, 2002Assignee: Infineon Technologies AGInventors: Paul-Werner Von Basse, Josef Willer, Thomas Scheiter, Stephan Marksteiner
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Patent number: 6309930Abstract: The SRAM cell arrangement comprises six MOS transistors per memory cell that are fashioned as vertical transistors. The MOS transistors are arranged at sidewalls of trenches (G1, G2, G4). Parts of the memory cell such as, for example, gate electrodes (Ga2, Ga4) or conductive structures (L3) fashioned as spacer are contacted via adjacent, horizontal, conductive structures (H5) arranged above a surface (O) of a substrate (S). Connections between parts of memory cells ensue via third conductive structures (L3) arranged at the sidewalls of the depressions and word lines (W) via diffusion regions (D2) that are adjacent to the sidewalls of the depressions within the substrate (S), via first bit lines, via second bit lines (B2) or/and via conductive structures (L1, L2, L6) that are partially arranged at different height with respect to an axis perpendicular to the surface (O). Contacts (K5) contact a plurality of parts of the MOS transistors simultaneously.Type: GrantFiled: November 9, 2000Date of Patent: October 30, 2001Assignee: Siemens AktiengesellschaftInventors: Bernd Goebel, Emmerich Bertagnolli, Josef Willer, Barbara Hasler, Paul-Werner von Basse
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Publication number: 20010022337Abstract: A grid-shaped array of conductor areas is used for capacitive image acquisition. Shielding conductors are disposed in each case between the conductors that are provided for measurement. During a plurality of charging and discharging cycles, the potential is always carried along on the conductors belonging to a respective pixel in order to prevent displacement currents between the shielding capacitors. By way of example, a compensation line with a feedback operational amplifier can be used for identically altering the electrical potentials on the conductors.Type: ApplicationFiled: February 13, 2001Publication date: September 20, 2001Inventors: Paul-Werner Von Basse, Josef Willer, Thomas Scheiter, Stephan Marksteiner
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Publication number: 20010019168Abstract: A semiconductor component with passivation includes at least two double passivating layers, of which an uppermost is applied to a planar surface of a layer located therebelow. The double passivating layers include two layers of different dielectric materials, for example silicon oxide and silicon nitride. The respective thicknesses of the individual passivating layers can be adapted to dimensions of the structuring of the layer to which the passivation is applied. This produces a reliable passivation which is particularly suitable for capacitively measuring fingerprint sensors.Type: ApplicationFiled: January 9, 2001Publication date: September 6, 2001Inventors: Josef Willer, Paul-Werner Von Basse, Thomas Scheiter
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Publication number: 20010017548Abstract: A grid of capacitor surfaces is connected to read lines and control lines. The read lines are connected alternately to the output of a feedback operational amplifier and to a collecting capacitor. The capacitances to be measured are charged repeatedly and the charges are collected on the collecting capacitors. Between the charging operations, the potential on the read lines is kept constant through the use of the low-resistance output of the operational amplifier. The use of this method in the case of a fingerprint sensor makes it possible to evaluate all the read lines together.Type: ApplicationFiled: January 23, 2001Publication date: August 30, 2001Inventors: Paul-Werner Von Basse, Josef Willer
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Patent number: 6222753Abstract: An SRAM cell arrangement which includes six MOS transistors per memory cell wherein each transistor is formed as a vertical transistors. The MOS transistors are arranged at sidewalls of trenches. Parts of the memory cell such as, for example, gate electrodes or conductive structures fashioned as spacers are contacted via adjacent, horizontal, conductive structures arranged above a surface of a substrate. Connections between parts of memory cells occur via third conductive structures arranged at the sidewalls of the depressions and word lines via diffusion regions that are adjacent to the sidewalls of the depressions within the substrate, via first bit lines, via second bit lines and/or via conductive structures that are partially arranged at different heights with respect to an axis perpendicular to the surface. Contacts contact a plurality of parts of the MOS transistors simultaneously.Type: GrantFiled: December 20, 1999Date of Patent: April 24, 2001Assignee: Siemens AktiengesellschaftInventors: Bernd Goebel, Emmerich Bertagnolli, Josef Willer, Barbara Hasler, Paul-Werner von Basse
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Patent number: 6181183Abstract: A circuit with a delay stage formed by an invertor having high-impedance transistors and, connected in series therewith, an invertor having low-impedance transistors MOS capacitors are provided between the gates of the transistors of the low-impedance invertor and the output of the delay stage. By means of this circuit, delay stages with steep edges can be realized with comparatively less outlay on components.Type: GrantFiled: March 18, 1999Date of Patent: January 30, 2001Assignee: Siemens AktiengesellschaftInventors: Paul-Werner Von Basse, Roland Thewes, Michael Bollu, Doris Schmitt-Landsiedel
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Patent number: 6153475Abstract: For the manufacture of a memory cell arrangement with first memory cells that comprise a vertical MOS transistor and with second memory cells that do not comprise an MOS transistor, whereby the memory cells are arranged along opposite edges of strip-type trenches, memory cells that are adjacent along the trenches (5) are manufactured successively. The spacing of adjacent memory cells is determined in particular by means of a spacer technology. By this means, a space requirement per memory cell of 1F.sup.2 can be realized, whereby F is the minimum structural size of the respective technology.Type: GrantFiled: June 21, 1999Date of Patent: November 28, 2000Assignee: Siemens AktiengesellschaftInventors: Franz Hofmann, Josef Willer, Hans Reisinger, Wolfgang Krautschneider, Paul-Werner von Basse
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Patent number: 6138227Abstract: A digital memory matrix having memory cells in rows and columns, addressing of the memory cells is accomplished by control devices which perform arbitrary jumps of address, thereby avoiding addressing on adjacent lines. The jump increment is selectable. The control devices are control chains, two of which are provided, and the outputs of the control chains are connected to linking elements that in turn are connected to the memory lines. The linking elements are provided in groups.Type: GrantFiled: March 13, 1998Date of Patent: October 24, 2000Assignee: Siemens AktiengesellschaftInventors: Roland Thewes, Doris Schmitt-Landsiedel, Paul-Werner von Basse, Michael Bollu
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Patent number: 6097661Abstract: In the pointer circuit, only one static memory (1) is respectively individually allocated to each output ( . . . , A.sub.n-1, A.sub.n, A.sub.n+1, . . . ), of which each respectively has a pair of mutually complementary memory terminals (Q, Q). The two terminals are in two stored logical states ("1," "0") differing from one another. A memory terminal (Q) of each memory is connected with the output allocated to this memory. The memories are controlled by clock signals. This results in advantageous surface requirement and power loss low, as well as high speed.Type: GrantFiled: September 25, 1998Date of Patent: August 1, 2000Assignee: Siemens AktiengesellschaftInventors: Roland Thewes, Doris Schmitt-Landsiedel, Paul-Werner von Basse, Michael Bollu, Ute Kollmer, Andreas Luck, deceased, by Manfred Luck, legal representative, by Inge Booken, legal representative
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Patent number: 6044006Abstract: Memory cells are organized in cell fields in word lines and bit lines in the manner of a matrix. The bit lines are actuated by a bit decoder for loading with a mass potential, and by a blocking decoder for loading the bit lines with a blocking potential. The word lines are actuated by a word decoder for loading the word lines with a programming voltage or a protective voltage. The information value to be programmed is prestored in the cell field.Type: GrantFiled: March 23, 1999Date of Patent: March 28, 2000Assignee: Siemens AktiengesellschaftInventors: Paul-Werner Von Basse, Roland Thewes, Doris Schmitt-Lansiedel, Michael Bollu