Abstract: A dynamic element matching system including sequential register groups, decode circuitry, and pointer control circuitry. Each register group includes at least two registers. The decode circuitry controls a state of each register group based on a level of a digital input signal, a relative position with respect to a begin pointer and an end pointer, and a corresponding one of multiple pseudo random probability values. The pointer control circuitry cyclically advances the end pointer among the register groups causing decode circuitry to add one or more register groups and enable a register within each added register group in response to the level of the digital input signal increasing, and also cyclically advances the begin pointer among the register groups causing the decode circuitry to remove one or more register groups and disable a register within each removed register group in response to the level of the digital input signal decreasing.

Abstract: A processor includes a register file having a plurality of register file addresses, a processing unit, configured to perform processing in accordance with a configuration defined by information stored in the register file, and an instruction sequencer. The instruction sequencer is configured to control the processing unit by retrieving a sequence of instructions from a memory, in which each instruction includes an opcode, and a subset of the instructions includes a data portion. For each instruction in the sequence of instructions, the instruction sequencer performs an action defined by the opcode. The action for the subset of the opcodes includes writing the data portion to a register file address defined by the opcode. The sequence of instructions includes variable length instructions.

Abstract: A method and apparatus of load detection for an audio amplifier system is described. A load detector includes a first load terminal and a second load terminal; a controller coupled to the first and second load terminals and configured to in a first control loop, vary a first current supplied to a first load terminal dependent on the difference between a first reference signal and the detected first load terminal voltage; and in a second control loop, vary a second current supplied to the second load terminal dependent on the difference between a second reference signal and the detected second load terminal voltage; and to determine a current through a load connected between the first load terminal and the second load terminal from the second current value, and a voltage across the load from the detected voltage difference between the first load terminal voltage and the second load terminal voltage.

Abstract: A method and apparatus of load detection for an audio amplifier system is described. A load detector includes a first load terminal and a second load terminal; a controller coupled to the first and second load terminals and configured to in a first control loop, vary a first current supplied to a first load terminal dependent on the difference between a first reference signal and the detected first load terminal voltage; and in a second control loop, vary a second current supplied to the second load terminal dependent on the difference between a second reference signal and the detected second load terminal voltage; and to determine a current through a load connected between the first load terminal and the second load terminal from the second current value, and a voltage across the load from the detected voltage difference between the first load terminal voltage and the second load terminal voltage.

Abstract: A SIMD parallel processor is described comprising an array comprising processing elements, associated data storage components and access means configured to enable access to at least one of the data storage components associated with at least one of the processing elements; a control processor; memory control means configured to enable addressing of at least one of the access means for the control processor; and connecting means configured to connect the memory control means to the access means.

Abstract: An asynchronous ripple pipeline has a plurality of stages, each with a controller (18) and a register (16). The controller has a register control output (21), and a combined acknowledgement and request output (20), together with a request input (22) and an acknowledgement input (24). The protocol used has a single signal, output on the combined acknowledgement and request output (20) of a stage (30), that functions both as a request to the next stage (32) and an acknowledgement to the previous stage (34).

Abstract: A SIMD parallel processor is described comprising an array comprising processing elements, associated data storage components and access means configured to enable access to at least one of the data storage components associated with at least one of the processing elements; a control processor; memory control means configured to enable addressing of at least one of the access means for the control processor; and connecting means configured to connect the memory control means to the access means.

Abstract: An electronic circuit has a data producing circuit (12), such as a matrix of memory cells. A capture circuit (14) has e an input coupled to the data producing circuit (10) for capturing the data signals after allowing a selected part of the data producing circuit to drive the input of the capture circuit. An error detection circuit (15) detects errors in the captured data signals. In response to detection of an error in particular data signals, the error detection circuit causes recapture of the particular data signals, allowing the data producing circuit (10) to drive the data signals at the input of the capture circuit (14) during a second time interval until recapture, the second time interval having a longer duration than the first time interval. This makes it possible to select the duration of the first time interval allowing for average driving speed of circuit parts (e.g. memory cells), without using a duration designed to account for worst case driving speed that may occur due to spread.

Abstract: A method testing an SRAM having a plurality of memory cells is disclosed. In a first step, a bit value is written into a cell under test (CUT). Subsequently, the first and second enabling transistors are disabled and the bit lines are discharged to a low potential. Next, the word line (WL) coupled to the memory cell under test is activated for a predetermined period. During a first part of this period, one of the bit lines (BLB) is kept at the low potential to force the associated pull up transistor in the CUT into a conductive state, after which this bit line (BLB) is charged to a high potential. Upon completion of this period, the bit value of the first cell is determined. The method facilitates the detection of weak or faulty SRAM cells without requiring the inclusion of dedicated hardware for this purpose.

Abstract: A circuit has a plurality of functional circuits (100a-f), each with multiphase control inputs. A control circuit drives the inputs for each phase in parallel. The control circuit (120a-c) comprises a chain of one-shot circuits (120a-c), each comprising a bi-stable circuit (121). The bi-stable circuit (121) of a first one-shot circuit in the chain has a set input coupled to the basic control signal input (126), the bi-stable circuits (121) of a remaining or each remaining one-shot circuit (120a-c) in the chain have a set input output of its predecessor in the chain. Each bi-stable circuit (121) has an output coupled to a respective one of the multiphase control outputs (14a-c) and a reset input coupled to the respective one of the multiphase control outputs (14a-c). Loading of the multiphase control outputs (14a-c) by the functional circuits results in a delay of the reset.

Abstract: A method testing an SRAM having a plurality of memory cells is disclosed. In a first step, a bit value is written into a cell under test (CUT). Subsequently, the first and second enabling transistors are disabled and the bit lines are discharged to a low potential. Next, the word line (WL) coupled to the memory cell under test is activated for a predetermined period. During a first part of this period, one of the bit lines (BLB) is kept at the low potential to force the associated pull up transistor in the CUT into a conductive state, after which this bit line (BLB) is charged to a high potential. Upon completion of this period, the bit value of the first cell is determined. The method facilitates the detection of weak or faulty SRAM cells without requiring the inclusion of dedicated hardware for this purpose.

Abstract: A circuit has a plurality of functional circuits (100a-f), each with multiphase control inputs. A control circuit drives the inputs for each phase in parallel. The control circuit (120a-c) comprises a chain of one-shot circuits (120a-c), each comprising a bi-stable circuit (121). The bi-stable circuit (121) of a first one-shot circuit in the chain has a set input coupled to the basic control signal input (126), the bi-stable circuits (121) of a remaining or each remaining one-shot circuit (120a-c) in the chain have a set input output of its predecessor in the chain. Each bi-stable circuit (121) has an output coupled to a respective one of the multiphase control outputs (14a-c) and a reset input coupled to the respective one of the multiphase control outputs (14a-c). Loading of the multiphase control outputs (14a-c) by the functional circuits results in a delay of the reset.

Abstract: In a method for data signal transfer across different clock-domains, including synchronization of a data signal with a current clock-domain where said data signal is processed, the processing of said data signal is started before the synchronization of said data signal is completed in said current clock-domain.

Abstract: An asynchronous ripple pipeline has a plurality of stages, each with a controller (18) and a register (16). The controller has a register control output (21), and a combined acknowledgement and request output (20), together with a request input (22) and an acknowledgement input (24). The protocol used has a single signal, output on the combined acknowledgement and request output (20) of a stage (30), that functions both as a request to the next stage (32) and an acknowledgement to the previous stage (34).

Abstract: An architecture for testing a pipeline (14) in an integrated circuit comprises an input port and an output port, and is operable to process a data word having a plurality of data bits. The architecture comprises a multiplexer (18) provided at each input of the input port of the pipeline (14), each multiplexer being operable to allow a data bit or test data bit to be input to the pipeline. A write test block (15) is operable to control the writing of data bits or test data bits to the pipeline (14) during a normal or test mode of operation, and a read test block (16) is operable to control the reading of data bits or test data bits from the pipeline during a normal or test mode of operation. The write test block (15) and the read test block (16) are operable in a test mode to control the pipeline (14) as a scan chain. The architecture requires less hardware and hence less silicon area than conventional test architectures.

Abstract: An electronic device is provided comprising a plurality of first shared resources (SR1-SR4) and a plurality of arbiter units (AAU1-AAU4) each for performing an arbitration for at least one of the plurality of shared resources (SR1-SR4). The communication between the arbiter units (AAU1-AAU4) is performed on an asynchronous basis, and the data communication between the first shared resources is performed on an asynchronous basis. Each arbiter unit (AAU1-AAU4) is adapted for sending a first token (T) to at least one neighboring arbiter unit (AAU1-AAU4), and for receiving a second token (T) from at least one neighboring arbiter unit (AAU1-AAU4) to implement a first global notion of time.

Abstract: A locally synchronous circuit module has a delay circuit having and input and output coupled to a clock input. The delay circuit provides a delay which when incorporated in a clock oscillator ensures a clock period that is at least as long as needed to transfer information between the storage elements. A handshake circuit is provided for generating handshake signals for timing information transfer between the locally synchronous circuit module and a further circuit. The handshake circuit comprises the delay circuit, so that at least part of the handshake signals during a handshake transaction are timed by traveling through the delay circuit and are applied to the clock input to clock the locally synchronous circuit module.

Abstract: A time-division multiplexing circuit-switching router comprises a plurality of input means (i1, . . . iN), at least one output means (o1, . . . , oM), switching means for switching between said input means (i1, . . . , iN) and said output means (o1, . . . , oM) and for connecting a selected input means to output means during a predetermined time slot, and a router table means for controlling said switching means, said router table means including instructions which input means be connected to output means for a predetermined time slot. Said router table means is divided into a plurality of tables, each table having a weight which specifies the amount of bandwidth per reservation in one table in relation to a reservation in the other table(s).

Abstract: A static latch (80) transfers input data (D) and its complement (DN) to an output terminal (100) and a complementary output terminal (98) when enabled and maintains the input data (D, DN) on the output terminals (100,98) when not enabled. The input data (D, DN) gate second and third transistors (86,88), the enable signal (G) gates a first transistor (90), such that when the latch (80) is enabled, the first and second transistors (98,86) and the first and third transistors (90,88) transfer the input data (D) and its complement (DN) to the specified output terminals (100,98) and when the latch (80) is disabled disconnects the input terminals (92,94) to maintain the current output values (Q,QN).

Abstract: A FIFO-register (10) according to the invention comprises a sequence of register cells (10.1, . . . ,10.m), which register cells have a data section (40) and a status section (30). Data (Din) provided at an input (20) is shifted via the data sections (40) in the register cells to an output (50). The status section (30) of each cell indicates whether the data section (40) of that cell contains valid data. The status section of a cell comprises a control unit (37) coupled to a status input (32), to a status output (33) and to a clock input (31), and generates an output clock signal (Cli), which controls charge controlling elements (35, 36) coupled to the status input and the status output and controls the data section (40). The status output (33) of a status section (30) and the status input (32?) of its successor (30?) share a common capacitive node (33).