Abstract: Method and apparatus for monitoring and controlling electrical current delivered to a computer subsystem are provided. One embodiment provides a method for detecting a short circuit in a computer subsystem, comprising: obtaining a measured current which is supplied to the computer subsystem during one or more time periods; determining an expected current utilized by the computer subsystem for the one or more time periods; and determining whether a short circuit condition exists based on a comparison between the measured current and the expected current. The method may further comprise terminating electrical power supplied to the computer subsystem.

Abstract: An inter-chip line transmission circuit in a transmitting chip and complementary receiving circuit in a receiving chip provide the capability to characterize the inter-chip interface by separately generating identical pseudo-random test data at both chips, comparing the data, and recording errors. Preferably, one or both chips can be tuned on an individual line basis to reduce errors by altering threshold detection voltage, signal delay, and/or driver power. The receiver circuit preferably contains counters for counting test cycles and errors, which can be masked for any particular line or type of error. A tunable and characterizable interface in accordance with the preferred embodiment thus supports the accurate determination of low error rates on an individual line basis for various tuning parameter settings.

Abstract: Method and apparatus for monitoring and controlling electrical current delivered to a computer subsystem are provided. One embodiment provides a method for detecting a short circuit in a computer subsystem, comprising: obtaining a measured current which is supplied to the computer subsystem during one or more time periods; determining an expected current utilized by the computer subsystem for the one or more time periods; and determining whether a short circuit condition exists based on a comparison between the measured current and the expected current. The method may further comprise terminating electrical power supplied to the computer subsystem.

Abstract: An inter-chip line transmission circuit in a transmitting chip and complementary receiving circuit in a receiving chip provide the capability to characterize the inter-chip interface by separately generating identical pseudo-random test data at both chips, comparing the data, and recording errors. Preferably, one or both chips can be tuned on an individual line basis to reduce errors by altering threshold detection voltage, signal delay, and/or driver power. The receiver circuit preferably contains counters for counting test cycles and errors, which can be masked for any particular line or type of error. A tunable and characterizable interface in accordance with the preferred embodiment thus supports the accurate determination of low error rates on an individual line basis for various tuning parameter settings.