Abstract: A data processor comprises a plurality of processing elements arranged for parallel processing of data, and a controller for controlling the plurality of processing elements.

Abstract: A controller for controlling a data processor having a plurality of processor arrays, each of which includes a plurality of processing elements, comprises a retrieval unit operable to retrieve a plurality of incoming instructions streams in parallel with one another, and a distribution unit operable to supply such incoming instruction streams to respective ones of the said plurality of processor arrays.

Abstract: A method for supplying instructions to a data processor having a plurality of processor arrays, each of which includes a plurality of processing elements, the method comprising retrieving instruction items for each of a plurality of instructions streams, each instruction stream having a plurality of instructions items, combining the plurality of instruction streams into a plurality of output instruction streams for supply to respective ones of the processor arrays, and distributing the output instruction streams to respective ones of the processor arrays.

Abstract: A data processor comprises a plurality of processing elements arranged in a first plurality of SIMD (single instruction multiple data) processing arrays, and comprises a second plurality of controllers for transferring instructions to the processing arrays. Each controller is operable to transfer at least one instruction stream, and to transfer received instruction streams to at least one of the first plurality of processing arrays.

Abstract: A data processing architecture comprising: an input device for receiving an incoming stream of data packets; and a plurality of processing elements which are operable to process data received thereby; wherein the input device is operable to distribute data packets in whole or in part to the processing elements in dependence upon the data processing bandwidth of the processing elements.

Abstract: A data processing architecture comprising: an input device for receiving an incoming stream of data packets; and a plurality of processing elements which are operable to process data received thereby; wherein the input device is operable to distribute data packets in whole or in part to the processing elements in dependence upon the data processing bandwidth of the processing elements.

Abstract: Apparatus for use in a computer system comprises a bus architecture, a plurality of modules connected to the bus architecture, at least one module being latency tolerant and at least one module being latency intolerant. The bus architecture comprises a primary bus (3) having latency intolerant modules connected thereto, a secondary bus (4) having latency tolerant modules connected thereto, and a primary to secondary bus interface module (5) interconnecting the primary and secondary buses.

Abstract: An interconnection system (110) interconnects a plurality of reusable functional units (105a), (105b), (105c). The system (110) comprises a plurality of nodes (135), (140), (145), (150), (155), (160) each node communicating with a functional unit. A plurality of data packets are transported between the functional units. Each data packet has routing information associated therewith to enable a node to direct the data packet via the interconnection system.

Abstract: A data processing architecture comprising:

Abstract: A data processing apparatus includes a SIMD (Single Instruction Multiple Data) array (10) of processing elements. The processing elements are operably divided into a plurality of processing blocks, the processing blocks being operable to process respective groups of data items.

Abstract: A post-processing method and apparatus to produce focus/defocus effects in computer generated images of three dimensional objects. A convolution filter stores pixel values (V) and associated depth values (Z) with a filter kernel being selected from a look-up table in dependence of the depth of the centre pixel (Z.sub.c) in relation to a specified focus depth (P). To minimize spurious effects where filter kernels overlap objects at different depths in the image, an inhibition function stage varies the amount by which each pixel contributes to the kernel in dependence on that pixel's depth value (Z) and the centre pixel and focus depth values (Z.sub.c and P). Inhibition profiles over a range of contributing and centre pixel values are provided.

Abstract: Moving output images are presented to a two dimensional display, such as a conventional television receiver (26). Three video sources are read from a compact disc, a notional front image and a notional back image being in the form of CD-I A and B planes. A notional back plane is a full frame, full video rate image, read from the disc as a coded MPEG data stream. After decoding, each pixel of each image includes depth data and opacity data. It is thus possible for an image in the notional front or notional middle plane to pass behind an object in the notional back plane. The depth and opacity data is severely compressed for the MPEG stream, by a process of quantisation and run-length encoding. The low resolution depth values for each pixel are converted to high resolution depth values via a look up table in order to further define the depth of each notional plane.

Abstract: The display apparatus includes a host processor having associated main memory, and a display processor (28', 49 etc.) having an associated texture memory (41') for storing a pyramidal or part-pyramidal array of texture element ("texel") values. Each pyramidal array includes a plurality of two-dimensional (2-D) arrays representing a 2-D modulation pattern at at least two distinct levels of resolution. The display processor further includes a circuit (28') for generating 2-D coordinate pairs (U1, V1) addressing texel values in a stored 2-D array, and 2-D interpolators (BIL1, BIL2) responsive to fractional parts (U1f, V1f) of the 2-D coordinate pairs for combining together a number of texel values from the addressed array so as to generate an interpolated texel value (MOD1). The apparatus further includes feedback (70,76 etc.

Abstract: A display apparatus includes a host processor (14) with associated main memory (24) and a display processor with associated display memory (30) and texture memory (41'). The host processor includes an arrangement (18) for storing in the texture memory (41') at least one pyramidal or part-pyramidal array of texel values representing a given texture at at least two levels of resolution defined by respective values of a level coordinate (L) and an arrangement (18) for supplying object primitive data to the display processor (28',49). The display processor includes a processing unit (28') for generating from the object primitive data a series of pixel addresses (X,Y) for application to the display memory (30) and a corresponding series of 2-D texture coordinate pairs (U,V) each with an associated level coordinate (L), to effect a mapping of the stored texture onto the object primitive at a level or levels of resolution defined by the level coordinate (L).

Abstract: An image of objects in a three dimensional space is generated for display on a two dimensional regular pixel array by offset and span generations (OFGN, SPGN) for anti-alias filtering which causes multiple rendition of the image, with each rendition displaced by a sub-pixel offset (Nx,Ny) with respect to the previous rendition. Image primitives are rendered by a scan line algorithm using a linked active polygon list (APL) and a deleted polygon list (DPL) to enable vertical offsets to be effected. The deleted polygon list stores primitives which would not be effective for a given line but for the offset to enable anti-alias filtering. These polygons would not normally be available for processing when using the scan line algorithm. Economical hardware (600) is provided for horizontal edge correction of parameters such as depth (z) and texture coordinates (u,v).

Abstract: Input data defines the address (X,Y), and an input color (RGB) and depth (Z) for a picture element (pixel) within a stored image. In order to perform hidden-surface removal (HSR), current depth values are stored for each pixel and compared with the input depth value to determine whether or not input data should be written to define a new color and depth for the pixel at (X,Y). The color and depth values are stored in a color RAM (9) and z-RAM (64). To obtain a speed advantage when modifying a series of consecutive pixels and one row of the RAMs, the current depth values are read and compared in advance for each pixel, during the writing period of one or more preceding pixels. The apparatus comprises a control and arithmetic unit (42), and a HSR control circuit (60) in addition to the color RAM (9) and z-RAM (64). The apparatus uses readily available video DRAM chips to provide a z-RAM with two data ports (62,66). The apparatus may form part of an electronic graphics system.