Abstract: A multiplier circuit is disclosed for multiplying a multiplicand by a multiplier. The multiplier circuit includes a partial product generator and a partial product adder. The partial product generator includes a first input to receive a multiplicand; a second input to receive a multiplier; partial product generation means for producing a plurality of partial products based on the multiplicand and the multiplier; and an output coupled to the partial product generation means to provide the plurality of partial products. The partial product adder includes an input coupled to the output of the partial product generator; a plurality of adders to add the plurality of partial products to produce a final product, the plurality of adders comprising a plurality of compressors having substantially the same width; and an output coupled to the plurality of adders to provide the final product.

Abstract: A memory block structure for use within a viterbi decoder includes multiple dual port RAMs configured as multiport RAMs. The memory block structure is configured to allow a one-word write operation and an N-word read operation during a single clock cycle in order to achieve one decoded output symbol per clock period using the viterbi algorithm. By using dual port RAMs, a more densely packed and less expensive memory block structure is achieved. An encoded stream of input symbols are input to the viterbi decoder and written to the memory block structure one word at a time. Once X+Y bits have been written to the memory block structure, the decoder will then read N words from the memory block structure, simultaneously, reading back through X+Y words and outputting Y bits N at a time at the end of the trace back through memory.