Abstract: A visualization system comprising a persistent memory, storing a dataset, and a non-persistent memory implements a pattern visualizing method. The dataset contains discrete attribute values for each first entity of a first type in a plurality of first entities of the first type and discrete attribute values for each first entity of a second type in a plurality of first entities of the second type for each second entity in a plurality of second entities. The dataset is compressed by blocked compression and represents discrete attribute values in both compressed sparse row and column formats. The discrete attribute values are clustered to assign each second entity to a cluster in a plurality of clusters.

Abstract: An apparatus for placement between a package and an integrated circuit board includes: an insert having: a substrate having a top side and a bottom side; a first set of pads at the top side of the substrate; a second set of pads at the bottom side of the substrate; and a plurality of vias in the substrate, the vias connecting respective pads in the first set to respective pads in the second set; wherein the insert has a thickness that is less than a spacing between the package and the integrated circuit board.

Abstract: In one embodiment, an integrated circuit (IC) includes a power distribution network having a first set of power distribution lines connected to a source voltage and a second set of power distribution lines connected to a ground voltage, and a first capacitor. A first variable resistive element is electrically coupled in series with the first capacitor between the first and second sets of power lines of the power distribution network. A control circuit is coupled to the variable resistive element and is configured and arranged to adjust a level of resistance of the first variable resistive element in response to an input signal. The adjustment of the level of resistance adjusts an equivalent series resistance of the power distribution network.

Abstract: An embodiment of an apparatus to reduce supply voltage noise with capacitors of an interposer of a stacked die is disclosed. In this embodiment, an interposer is coupled to a first integrated circuit die using a first plurality of interconnects. A substrate is coupled to the interposer using a second plurality of interconnects. The substrate includes a supply voltage plane and a ground plane, each of which is coupled to the first integrated circuit die using the second plurality of interconnects, the interposer, and the first plurality of interconnects. The interposer includes capacitors coupled in parallel using the supply voltage plane, the ground plane, and the second plurality of interconnects, where capacitance from capacitors of the interposer is provided to the first integrated circuit die using the supply voltage plane and the ground plane of the substrate.

Abstract: Embodiments of the invention generally provide an electronic device comprising an electrical interconnect component that includes an electrical trace. The electrical trace has geometric characteristics that serve to suppress the skin effect over a large band of frequency components. More specifically, the electrical trace has a thickness that is less than a skin depth for a particular chosen frequency component. By making the electrical trace have a thickness that is less than the skin depth, the current flows through substantially the entire cross-sectional area of the electrical trace for all frequencies up to the chosen frequency component, which reduces the effects associated with the skin effect.

Abstract: An electrical circuit structure can include a first trace formed using a first conductive layer and a second trace formed using a second conductive layer. The first trace can be vertically aligned with the second trace. The electrical circuit structure can include a via segment formed of conductive material in a third conductive layer between the first conductive layer and the second conductive layer. The via segment can contact the first trace and the second trace forming a first conductor structure configured to convey an electrical signal in a direction parallel to the first conductive layer.

Abstract: An apparatus for placement between a package and an integrated circuit board includes: an insert having: a substrate having a top side and a bottom side; a first set of pads at the top side of the substrate; a second set of pads at the bottom side of the substrate; and a plurality of vias in the substrate, the vias connecting respective pads in the first set to respective pads in the second set; wherein the insert has a thickness that is less than a spacing between the package and the integrated circuit board.

Abstract: A semiconductor device includes a first under-bump metallization (UBM) layer disposed over a bond pad, a dielectric layer above an interconnect layer having a via exposing at least a portion of the first UBM layer. A second UBM layer is disposed above the first UBM layer and forms a UBM bucket over the via. The first UBM layer and UBM bucket are configured to support a solder ball and can advantageously block all alpha particles emitted by the solder ball having a relevant angle of incidence from reaching the active semiconductor regions of the IC. Thus, soft errors, such as single event upsets in memory cells, are reduced or eliminated.

Abstract: An integrated circuit includes a stacked conductive layer interposer and a first die at least partially encapsulated in a mold material. The first die is mechanically and electrically attached to a top surface of the stacked conductive layer interposer using solder bumps. The integrated circuit further includes a first warpage correction layer.

Abstract: An interconnect array is described. The interconnect array comprises a pattern of adjacent interconnect tiles, each interconnect tile comprising ten interconnect locations including eight I/O signal connectivity locations forming a perimeter array having a corner I/O signal connectivity location, a center connectivity location surrounded by the eight I/O signal connectivity locations in the perimeter array being a first ground connectivity location or a power connectivity location, and a second ground connectivity location adjacent to the corner I/O signal connectivity location of the perimeter array and externally offset from the perimeter array to form an asymmetrically shaped interconnect tile. At least one interconnect tile of the pattern of adjacent interconnect tiles has a center connectivity location that is a power connectivity location.

Abstract: An electrical circuit structure can include a first trace formed using a first conductive layer and a second trace formed using a second conductive layer. The first trace can be vertically aligned with the second trace. The electrical circuit structure can include a via segment formed of conductive material in a third conductive layer between the first conductive layer and the second conductive layer. The via segment can contact the first trace and the second trace forming a first conductor structure configured to convey an electrical signal in a direction parallel to the first conductive layer.

Abstract: A silicon substrate has a conductive via extending from a first surface of the silicon substrate through the silicon substrate to a second surface of the silicon substrate. A dielectric via extends from the second surface of the silicon substrate toward the first surface of the silicon substrate.

Abstract: An integrated circuit (IC) structure can include an internal element and a flexible circuitry directly coupled to the internal element. The flexible circuitry can be configured to exchange signals between the internal element and a node external to the IC structure.

Abstract: In one embodiment, an integrated circuit (IC) is presented. The IC includes first and second sets of power distribution lines formed in the IC. The IC includes first and second capacitors formed in one or more layers of the IC. A first plurality of vias couple a first input of the first and second capacitors to the first set of power distribution lines, and a second plurality of vias couple a second input of the first and second capacitors to the second set of power distribution lines. The first capacitor and the first plurality of vias and the second plurality of vias coupled thereto having an equivalent series resistance greater than an equivalent series resistance of the second capacitor and the first plurality of vias and the second plurality of vias coupled thereto.

Abstract: In one embodiment, an integrated circuit (IC) is presented. The IC includes first and second sets of power distribution lines formed in the IC. The IC includes first and second capacitors formed in one or more layers of the IC. A first plurality of vias couple a first input of the first and second capacitors to the first set of power distribution lines, and a second plurality of vias couple a second input of the first and second capacitors to the second set of power distribution lines. The first capacitor and the first plurality of vias and the second plurality of vias coupled thereto having an equivalent series resistance greater than an equivalent series resistance of the second capacitor and the first plurality of vias and the second plurality of vias coupled thereto.

Abstract: A semiconductor device package and methods of manufacturing the same are described. In some examples, a semiconductor device includes an IC die including a ring of die pads around a periphery thereof, lands disposed within the ring of die pads, bond terminals coupled to the lands, the bond terminals being wire-bonded to respective ones of the die pads, and at least one capacitor having respective terminals mounted to respective ones of the lands.

Abstract: A silicon substrate has a conductive via extending from a first surface of the silicon substrate through the silicon substrate to a second surface of the silicon substrate. A dielectric via extends from the second surface of the silicon substrate toward the first surface of the silicon substrate.

Abstract: A device has a silicon substrate with a via extending from a first surface of the silicon substrate having a conductor portion. A first dielectric portion surrounds the conductor portion. A second dielectric portion is disposed between a first silicon portion and the silicon substrate.

Abstract: An embodiment of a method of forming a semiconductor device that includes a substrate having an active layer and interconnect formed on the active layer is described. The method includes: forming a dielectric layer above the interconnect having a tapered via exposing at least a portion of a first metal layer; forming an under-bump metallization (UBM) layer over the tapered via and the first metal layer to form a UBM bucket; and forming a dielectric cap layer over the dielectric layer and a portion of the UBM layer. The UBM bucket is configured to support a solder ball and can advantageously block all alpha particles emitted by the solder ball having a relevant angle of incidence from reaching the active semiconductor regions of the IC. Thus, soft errors, such as single event upsets in memory cells, are reduced or eliminated.