Abstract: Encryption and decryption techniques based on one or more transposition vectors. A secret key is used to generate vectors that describe permutation (or repositioning) of characters within a segment length equal to a length of the transposition vector. The transposition vector is then inherited by the encryption process, which shifts characters and encrypts those characters using a variety of encryption processes, all completely reversible. In one embodiment, one or more auxiliary keys, transmitted as clear text header values, are used as initial values to vary the transposition vectors generated from the secret key, e.g., from encryption-to-encryption. Any number of rounds of encryption can be applied, each having associated headers used to “detokenize” encryption data and perform rounds to decryption to recover the original data (or parent token information). Format preserving encryption (FPE) techniques are also provided with application to, e.g., payment processing.

Abstract: Encryption and decryption techniques based on one or more transposition vectors. A secret key is used to generate vectors that describe permutation (or repositioning) of characters within a segment length equal to a length of the transposition vector. The transposition vector is then inherited by the encryption process, which shifts characters and encrypts those characters using a variety of encryption processes, all completely reversible. In one embodiment, one or more auxiliary keys, transmitted as clear text header values, are used as initial values to vary the transposition vectors generated from the secret key, e.g., from encryption-to-encryption. Any number of rounds of encryption can be applied, each having associated headers used to “detokenize” encryption data and perform rounds to decryption to recover the original data (or parent token information). Format preserving encryption (FPE) techniques are also provided with application to, e.g., payment processing.

Abstract: An interconnect array uses repeated application of an interconnect pattern (“tile”). The tile has eight I/O signal pins forming a perimeter array, a central pin that can be either a ground pin or an I/O power pin, and an offset ground pin. The I/O signal pins are associated with the same or multiple I/O banks. If the central pin is an I/O power pin, it is optionally associated with an I/O bank associated with one or more of the I/O signal pins.

Abstract: An integrated circuit device having a multi-layer substrate coupled to receive an integrated circuit die and enabling fixed voltage reference signals of a power distribution network and input/output signals to be routed in the integrated circuit device. The multi-layer substrate comprises a first metal layer comprising a reference signal plane of coupling a first fixed voltage reference signal; a dielectric layer positioned on the first metal layer; and a second metal layer having a plurality of conductive traces, wherein the plurality of conductive traces comprise conductive traces for coupling a second fixed reference signal and input/output signals. The plurality of conductive traces may be in a predetermined pattern having reference signal traces and input/output signal traces. A method of enabling different signals comprising reference signals and input/output signals to be routed in a multi-layer substrate adapted to receive a die in an integrated circuit is also disclosed.

Abstract: Composite flip-chip with encased components and method of fabricating the same is described. One aspect of the invention relates to fabricating composite flip-chip packages for integrated circuit dice. Interposing substrates are formed. At least one discrete component is attached to a bottom surface of each of the interposing substrates. A first array of solder balls is placed on the bottom surface of each of the interposing substrates. The interposing substrates are mounted to a carrier strip. The integrated circuit dice are attached to top surfaces of the interposing substrates. The integrated circuit dice and the interposing substrates are encapsulated in molding compound to define flip-chip assemblies.

Abstract: A method and apparatus is provided to reduce the spreading inductance and increase the distributed capacitance of power planes within the power distribution system of a semiconductor package substrate. In one embodiment, pre-fabricated copper-clad laminate (CCL) structures are utilized as starting material for the power plane pairs, which are then integrated into a package substrate using imaging, lamination, and drilling/plating processes. In alternate embodiments, a starting material having a larger insulating layer thickness may be used to form the CCL structure, whereby a pair of metallic planes having a perforated mesh pattern are adjoined through a dielectric layer to create an effective separation distance between the metallic planes. Alternate embodiments employ plating or deposition methods to obtain a minimum separation distance between the metallic planes of a power plane pair.

Abstract: A packaged integrated circuit (“IC”) includes a substrate, an IC die, and a molded plastic lid. A test point standoff is electrically connected to the IC die and extends away from the surface of the package substrate through the molded plastic lid toward the top surface of the molded plastic lid. The top of the test point standoff is below the top surface of the molded plastic lid.

Abstract: Methods of manufacturing a family of packaged integrated circuits (ICs) having at least two different logic capacities. A first IC die includes two different portions, of which at least one portion can be deliberately rendered non-operational in some manner (e.g., non-functional, inaccessible, and/or non-programmable) within the package. A first set of the first IC dies are packaged such that both portions of the dies are operational. A second set of the first IC dies are packaged such that only the first portion of each die is operational. Once the first and second sets are packaged and the second set of ICs has been evaluated, a decision is made whether or not to manufacture a second IC die that includes the first portion of the first die, while excluding the second portion.

Abstract: An integrated circuit die (e.g., a programmable logic device (PLD) die) is manufactured that has the capability of being configured as at least two differently-sized family members. The IC die is tested prior to packaging. If a first portion of the IC die is fully functional, but a second portion includes a localized defect, then the IC die is packaged with a product selection code that configures the IC die to operate as only the first portion of the die. The second portion of the die is deliberately rendered non-operational. Therefore, the IC die can still be sold as a fully functional packaged IC.

Abstract: A lid having a plurality of recesses at the edges of the lid to provide an improved adhesive bond between the lid and a substrate of an integrated circuit is disclosed. The plurality of recesses may be a castellation comprising a collection of semi-circular cuts into the originally straight edges of the lid. The castellation can be formed by stamping, etching, molding design, or milling/drilling, all of which are well-known methods in the art of forming lids for integrated circuits. The castellation can be vertically straight or it can be slightly tapered, to provide a better locking of the lid on to the package. Epoxy in the recesses can provide an epoxy post for locking the lid. Method of forming a lid having a plurality of recesses and employing a lid on an integrated circuit are also disclosed.

Abstract: Composite flip-chip with encased components and method of fabricating the same is described. One aspect of the invention relates to fabricating composite flip-chip packages for integrated circuit dice. Interposing substrates are formed. At least one discrete component is attached to a bottom surface of each of the interposing substrates. A first array of solder balls is placed on the bottom surface of each of the interposing substrates. The interposing substrates are mounted to a carrier strip. The integrated circuit dice are attached to top surfaces of the interposing substrates. The integrated circuit dice and the interposing substrates are encapsulated in molding compound to define flip-chip assemblies.

Abstract: A multi-product integrated circuit die includes at least two different portions, of which at least one portion can be deliberately rendered non-operational in some manner (e.g., non-functional, inaccessible, and/or non-programmable) within the package. A selection code storage circuit stores a product selection code. A first value of the product selection code selects the option where both the first and second portions of the first die are operational. A second value of the product selection code selects the option where only the first portion of the first die is operational. The selection code storage circuit can include non-volatile memory or a fuse structure, or the product selection code can be configured as a package bonding option. The product selection code can also enable boundary scan for the operational portion of the die, and omit from the boundary scan chain any portions of the die that are deliberately rendered non-operational.

Abstract: A semiconductor structure includes a carrier having a cavity formed in a top portion thereof, and a plurality of conductive contacts formed on a top surface of the carrier and positioned around the periphery of the cavity. A number of first coplanar dice are back-side mounted to a top surface of the cavity, and a number of second coplanar dice are flip-chip mounted to the first dice, wherein each of the first dice is electrically connected to two corresponding adjacent second dice to connect the dice in a cascade configuration. For some embodiments, selected dice are flip-chip mounted to the carrier. For other embodiments, selected dice are wire-bond connected to the carrier.

Abstract: A method of producing a wirebond ball grid array package is described. The method comprises the steps of importing a master pinlist to a computer program, importing a bonding diagram to the computer program, and verifying, by the computer program, substrate artwork against the master pinlist and the bonding diagram. A method of producing a wirebond ball grid array package according to an alternative embodiment comprises the steps of importing a master pinlist to a computer program, importing substrate artwork to the computer program, and verifying, by the computer program, a bonding diagram against the master pinlist and the substrate artwork. Finally, a system for verifying substrate artwork comprises means for importing a master pinlist to a computer program, means for importing a bonding diagram to the computer program, and means for verifying, by the computer program, the substrate artwork against the master pinlist and the bonding diagram.

Abstract: A lid having a plurality of recesses at the edges of the lid to provide an improved adhesive bond between the lid and a substrate of an integrated circuit is disclosed. The plurality of recesses may be a castellation comprising a collection of semi-circular cuts into the originally straight edges of the lid. The castellation can be formed by stamping, etching, molding design, or milling/drilling, all of which are well-known methods in the art of forming lids for integrated circuits. The castellation can be vertically straight or it can be slightly tapered, to provide a better locking of the lid on to the package. Epoxy in the recesses can provide an epoxy post for locking the lid. Method of forming a lid having a plurality of recesses and employing a lid on an integrated circuit are also disclosed.

Abstract: A computer pointing device that functions electronically as a mouse with a preferred shape that looks like the top of an upright hawk, permitting ergonomic holding by the whole palm in a naturally upright position during operation, including moving the cursor, turning the scroll wheel, and clicking the buttons.

Abstract: A computer pointing device that functions electronically as a mouse with a preferred shape that looks like the top of an upright hawk, permitting ergonomic holding by the whole palm in a naturally upright position during operation, including moving the cursor, turning the scroll wheel, and clicking the buttons.