Patents by Inventor Paula C. Kiser

Paula C. Kiser has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7131032
    Abstract: Provided are a method, system and article of manufacture for fault determination. A duration of time is determined for receiving an event. A plurality of events are received in a time period that is at least twice the determined duration. A plurality of factors are determined corresponding to the plurality of events. At least one factor is determined from the plurality of factors, wherein the at least one factor is a cause of at least one of the plurality of events.
    Type: Grant
    Filed: March 13, 2003
    Date of Patent: October 31, 2006
    Assignee: Sun Microsystems, Inc.
    Inventors: Gavin G. Gibson, Todd H. McKenney, Christian Cadieux, Paula C. Kiser
  • Publication number: 20040181709
    Abstract: Provided are a method, system and article of manufacture for fault determination. A duration of time is determined for receiving an event. A plurality of events are received in a time period that is at least twice the determined duration. A plurality of factors are determined corresponding to the plurality of events. At least one factor is determined from the plurality of factors, wherein the at least one factor is a cause of at least one of the plurality of events.
    Type: Application
    Filed: March 13, 2003
    Publication date: September 16, 2004
    Applicant: Sun Microsystems, Inc.
    Inventors: Gavin G. Gibson, Todd H. McKenney, Christian Cadieux, Paula C. Kiser
  • Patent number: 6356984
    Abstract: A digital data processing system comprises at least one subsystem comprising a plurality of resources, such as a storage subsystem comprising a plurality of drive modules, and a host processor. The host processor is connected to the drive modules through an interconnection which has a topology in the form of a loop. The interconnection has at least one configuration switch that is selectively configurable to a pass-through mode, in which the topology comprises the entire loop, or a bypass mode, in which the topology comprises a portion of the loop including the host processor and, possibly, at least one of the drive modules in the storage subsystem. The host processor can selectively condition the configuration switch into the pass-through mode or said bypass mode to connect more or fewer drive modules into the loop.
    Type: Grant
    Filed: June 30, 1998
    Date of Patent: March 12, 2002
    Assignee: Sun Microsystems, Inc.
    Inventors: William F. Day, Susan L. Copeland, David A. Hill, Mark J. Hornacek, Michael K. Hosrom, Gavin J. Kirton, Paula C. Kiser