Abstract: Technical solutions are described for reducing page invalidation broadcasts in a computer system. An example method includes pre-allocating a pool of large memory frames by a real storage manager. The method also includes receiving, by a virtual storage manager, an instruction from an application to allocate a memory buffer, where the instruction includes a request to back the memory buffer using large pages. The virtual storage manager, in response to the instruction, allocates the memory buffer from the pre-allocated pool of large memory frames.

Abstract: Technical solutions for providing real time analytics of a private area of a virtual address space are described. One general aspect includes a method that includes determining, by a processor, a start address and a size of the private area of the virtual address space. The method also includes determining, by the processor, a highest address corresponding to a user region of the private area. The method also includes determining, by the processor, a lowest address corresponding to a high-end region of the private area. The method also includes storing, by the processor, the determined information in a common area outside the virtual address space.

Abstract: Technical solutions for providing real time analytics of a private area of a virtual address space are described. One general aspect includes a method that includes determining, by a processor, a start address and a size of the private area of the virtual address space. The method also includes determining, by the processor, a highest address corresponding to a user region of the private area. The method also includes determining, by the processor, a lowest address corresponding to a high-end region of the private area. The method also includes storing, by the processor, the determined information in a common area outside the virtual address space.

Abstract: Technical solutions are described for reducing page invalidation broadcasts in a computer system. An example method includes pre-allocating a pool of large memory frames by a real storage manager. The method also includes receiving, by a virtual storage manager, an instruction from an application to allocate a memory buffer, where the instruction includes a request to back the memory buffer using large pages. The virtual storage manager, in response to the instruction, allocates the memory buffer from the pre-allocated pool of large memory frames.

Abstract: Technical solutions for providing real time analytics of a private area of a virtual address space are described. One general aspect includes a method that includes determining, by a processor, a start address and a size of the private area of the virtual address space. The method also includes determining, by the processor, a highest address corresponding to a user region of the private area. The method also includes determining, by the processor, a lowest address corresponding to a high-end region of the private area. The method also includes storing, by the processor, the determined information in a common area outside the virtual address space.

Abstract: Technical solutions for providing real time analytics of a private area of a virtual address space are described. One general aspect includes a method that includes determining, by a processor, a start address and a size of the private area of the virtual address space. The method also includes determining, by the processor, a highest address corresponding to a user region of the private area. The method also includes determining, by the processor, a lowest address corresponding to a high-end region of the private area. The method also includes storing, by the processor, the determined information in a common area outside the virtual address space.

Abstract: A computer system includes a translation look-aside (TLB) buffer and a processing unit. The TLB is configured to store an entry that comprises virtual address information, real address information associated with the virtual address information, and additional information corresponding to at least one of the virtual address information and the real address information. The processing unit is configured to control the TLB to modify the additional information while maintaining the entry in a valid state accessible by the processing unit for a translation look-aside operation corresponding to the virtual address information and the real address information.

Abstract: A fault occurs in a virtual environment that includes a base space, a first subspace, and a second subspace, each with a virtual address associated with content in auxiliary storage memory. The fault is resolved by copying the content from auxiliary storage to central storage memory and updating one or more base space dynamic address translation (DAT) tables, and not updating DAT tables of the first and second subspace. A subsequent fault at the first subspace virtual address is resolved by copying the base space DAT table information to the first subspace DAT tables and not updating the second subspace DAT tables. A fault occurring with association to the virtual address of the first subspace is resolved for the base space and the base space DAT table information is copied to the first subspace DAT tables, and the second subspace DAT tables are not updated.

Abstract: A fault occurs in a virtual environment that includes a base space, a first subspace, and a second subspace, each with a virtual address associated with content in auxiliary storage memory. The fault is resolved by copying the content from auxiliary storage to central storage memory and updating one or more base space dynamic address translation (DAT) tables, and not updating DAT tables of the first and second subspace. A subsequent fault at the first subspace virtual address is resolved by copying the base space DAT table information to the first subspace DAT tables and not updating the second subspace DAT tables. A fault occurring with association to the virtual address of the first subspace is resolved for the base space and the base space DAT table information is copied to the first subspace DAT tables, and the second subspace DAT tables are not updated.

Abstract: A computer system includes a translation look-aside (TLB) buffer and a processing unit. The TLB is configured to store an entry that comprises virtual address information, real address information associated with the virtual address information, and additional information corresponding to at least one of the virtual address information and the real address information. The processing unit is configured to control the TLB to modify the additional information while maintaining the entry in a valid state accessible by the processing unit for a translation look-aside operation corresponding to the virtual address information and the real address information.

Abstract: A virtual storage technique is provided to manage a cell pool or a set of cell pools which can be used to satisfy variable-size storage requests. The algorithm uses no locks and relies on an atomic compare-and-swap instruction to serialize updates to the fields that can be simultaneously requested by multiple threads or processes. A free chain is used to manage cells which have already been obtained and freed, while there is an active extent that is used to hand out cells which have not previously been obtained. The algorithm is based on all cell pool extents being the same size, which allows the control information for the extent to be easily located on the extent boundary (e.g. at a 1 MB boundary). Control information for each cell is stored independently of the cell storage in a control array that resides at the head of the extent, along with other control information. This avoids cell overrun from damaging the cell pool control information.