Patents by Inventor Pauli Jaervinen

Pauli Jaervinen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12237305
    Abstract: Embodiments of the present disclosure are directed towards an integrated circuit (IC) package including a first die at least partially embedded in a first encapsulation layer and a second die at least partially embedded in a second encapsulation layer. The first die may have a first plurality of die-level interconnect structures disposed at a first side of the first encapsulation layer. The IC package may also include a plurality of electrical routing features at least partially embedded in the first encapsulation layer and configured to route electrical signals between a first and second side of the first encapsulation layer. The second side may be disposed opposite to the first side. The second die may have a second plurality of die-level interconnect structures that may be electrically coupled with at least a subset of the plurality of electrical routing features by bonding wires.
    Type: Grant
    Filed: September 30, 2022
    Date of Patent: February 25, 2025
    Inventors: Thorsten Meyer, Pauli Jaervinen, Richard Patten
  • Publication number: 20230023328
    Abstract: Embodiments of the present disclosure are directed towards an integrated circuit (IC) package including a first die at least partially embedded in a first encapsulation layer and a second die at least partially embedded in a second encapsulation layer. The first die may have a first plurality of die-level interconnect structures disposed at a first side of the first encapsulation layer. The IC package may also include a plurality of electrical routing features at least partially embedded in the first encapsulation layer and configured to route electrical signals between a first and second side of the first encapsulation layer. The second side may be disposed opposite to the first side. The second die may have a second plurality of die-level interconnect structures that may be electrically coupled with at least a subset of the plurality of electrical routing features by bonding wires.
    Type: Application
    Filed: September 30, 2022
    Publication date: January 26, 2023
    Inventors: Thorsten Meyer, Pauli Jaervinen, Richard Patten
  • Patent number: 10319688
    Abstract: An antenna is described on ceramics that may be used for a packaged die. In one example, a package has a die, a ceramic substrate over the die, an antenna attached to the ceramic substrate, and conductive leads electrically connecting the antenna to the die.
    Type: Grant
    Filed: December 9, 2013
    Date of Patent: June 11, 2019
    Assignee: Intel Corporation
    Inventors: Andreas Wolter, Saravana Maruthamuthu, Mikael Knudsen, Thorsten Meyer, Georg Seidemann, Pablo Herrero, Pauli Jaervinen
  • Patent number: 10249598
    Abstract: Embodiments of the present disclosure are directed towards an integrated circuit (IC) package including a first die at least partially embedded in a first encapsulation layer and a second die at least partially embedded in a second encapsulation layer. The first die may have a first plurality of die-level interconnect structures disposed at a first side of the first encapsulation layer. The IC package may also include a plurality of electrical routing features at least partially embedded in the first encapsulation layer and configured to route electrical signals between a first and second side of the first encapsulation layer. The second side may be disposed opposite to the first side. The second die may have a second plurality of die-level interconnect structures that may be electrically coupled with at least a subset of the plurality of electrical routing features by bonding wires.
    Type: Grant
    Filed: March 8, 2018
    Date of Patent: April 2, 2019
    Assignee: Intel Corporation
    Inventors: Thorsten Meyer, Pauli Jaervinen, Richard Patten
  • Publication number: 20180315737
    Abstract: Embodiments of the present disclosure are directed towards an integrated circuit (IC) package including a first die at least partially embedded in a first encapsulation layer and a second die at least partially embedded in a second encapsulation layer. The first die may have a first plurality of die-level interconnect structures disposed at a first side of the first encapsulation layer. The IC package may also include a plurality of electrical routing features at least partially embedded in the first encapsulation layer and configured to route electrical signals between a first and second side of the first encapsulation layer. The second side may be disposed opposite to the first side. The second die may have a second plurality of die-level interconnect structures that may be electrically coupled with at least a subset of the plurality of electrical routing features by bonding wires.
    Type: Application
    Filed: July 6, 2018
    Publication date: November 1, 2018
    Inventors: Thorsten Meyer, Pauli Jaervinen, Richard Patten
  • Publication number: 20180197840
    Abstract: Embodiments of the present disclosure are directed towards an integrated circuit (IC) package including a first die at least partially embedded in a first encapsulation layer and a second die at least partially embedded in a second encapsulation layer. The first die may have a first plurality of die-level interconnect structures disposed at a first side of the first encapsulation layer. The IC package may also include a plurality of electrical routing features at least partially embedded in the first encapsulation layer and configured to route electrical signals between a first and second side of the first encapsulation layer. The second side may be disposed opposite to the first side. The second die may have a second plurality of die-level interconnect structures that may be electrically coupled with at least a subset of the plurality of electrical routing features by bonding wires.
    Type: Application
    Filed: March 8, 2018
    Publication date: July 12, 2018
    Inventors: Thorsten Meyer, Pauli Jaervinen, Richard Patten
  • Patent number: 9972601
    Abstract: Embodiments of the present disclosure are directed towards an integrated circuit (IC) package including a first die at least partially embedded in a first encapsulation layer and a second die at least partially embedded in a second encapsulation layer. The first die may have a first plurality of die-level interconnect structures disposed at a first side of the first encapsulation layer. The IC package may also include a plurality of electrical routing features at least partially embedded in the first encapsulation layer and configured to route electrical signals between a first and second side of the first encapsulation layer. The second side may be disposed opposite to the first side. The second die may have a second plurality of die-level interconnect structures that may be electrically coupled with at least a subset of the plurality of electrical routing features by bonding wires.
    Type: Grant
    Filed: September 26, 2014
    Date of Patent: May 15, 2018
    Assignee: INTEL CORPORATION
    Inventors: Thorsten Meyer, Pauli Jaervinen, Richard Patten
  • Patent number: 9819327
    Abstract: Techniques and configurations are disclosed for bulk acoustic wave resonator (BAWR) tuner circuits and their use in integrated circuit (IC) packages and mobile communication devices for radio frequency (RF) communication. In some embodiments, a mobile communication device may include an antenna; a transmitter circuit having an output port, a tuner circuit having one or more BAWRs, an antenna port coupled to the antenna, a transmitter port coupled to the output port of the transmitter circuit, and a control port; and a control circuit, coupled to the control port, configured to adjust an impedance of the tuner circuit, via adjustment of a BAWR or another component of the tuner circuit, based at least in part on an impedance of the antenna. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: June 26, 2013
    Date of Patent: November 14, 2017
    Assignee: INTEL IP CORPORATION
    Inventors: Saravana Maruthamuthu, Thorsten Meyer, Pablo Herrero, Andreas Wolter, Georg Seidemann, Mikael Knudsen, Pauli Jaervinen
  • Publication number: 20160276311
    Abstract: Embodiments of the present disclosure are directed towards an integrated circuit (IC) package including a first die at least partially embedded in a first encapsulation layer and a second die at least partially embedded in a second encapsulation layer. The first die may have a first plurality of die-level interconnect structures disposed at a first side of the first encapsulation layer. The IC package may also include a plurality of electrical routing features at least partially embedded in the first encapsulation layer and configured to route electrical signals between a first and second side of the first encapsulation layer. The second side may be disposed opposite to the first side. The second die may have a second plurality of die-level interconnect structures that may be electrically coupled with at least a subset of the plurality of electrical routing features by bonding wires.
    Type: Application
    Filed: August 26, 2014
    Publication date: September 22, 2016
    Applicant: INTEL CORPORATION
    Inventors: Thorsten Meyer, Pauli Jaervinen, Richard Patten
  • Publication number: 20160240492
    Abstract: An antenna is described on ceramics that may be used for a packaged die. In one example, a package has a die, a ceramic substrate over the die, an antenna attached to the ceramic substrate, and conductive leads electrically connecting the antenna to the die.
    Type: Application
    Filed: December 9, 2013
    Publication date: August 18, 2016
    Inventors: Andreas Wolter, Saravana Maruthamuthu, Mikael Knudsen, Meyer Thorsten, Georg Seidemann, Pablo Herrero, Pauli Jaervinen
  • Publication number: 20150333401
    Abstract: Techniques and configurations are disclosed for bulk acoustic wave resonator (BAWR) tuner circuits and their use in integrated circuit (IC) packages and mobile communication devices for radio frequency (RF) communication. In some embodiments, a mobile communication device may include an antenna; a transmitter circuit having an output port, a tuner circuit having one or more BAWRs, an antenna port coupled to the antenna, a transmitter port coupled to the output port of the transmitter circuit, and a control port; and a control circuit, coupled to the control port, configured to adjust an impedance of the tuner circuit, via adjustment of a BAWR or another component of the tuner circuit, based at least in part on an impedance of the antenna. Other embodiments may be described and/or claimed.
    Type: Application
    Filed: June 26, 2013
    Publication date: November 19, 2015
    Inventors: Saravana MARUTHAMUTHU, Thorsten MEYER, Pablo HERRERO, Andreas WOLTER, Georg SEIDEMANN, Mikael KNUDSEN, Pauli JAERVINEN
  • Patent number: 8779564
    Abstract: A semiconductor device may include: a chip; a chip packaging structure at least partially surrounding the chip and having a receiving region configured to receive a first capacitive coupling structure; a first capacitive coupling structure disposed in the receiving region; and a second capacitive coupling structure disposed over the first capacitive coupling structure and capacitively coupled to the first capacitive coupling structure.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: July 15, 2014
    Assignee: Intel IP Corporation
    Inventors: Mikael Knudsen, Thorsten Meyer, Saravana Maruthamuthu, Andreas Wolter, Georg Seidemann, Pablo Herrero, Pauli Jaervinen