Patents by Inventor Pauli Jaervinen
Pauli Jaervinen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12237305Abstract: Embodiments of the present disclosure are directed towards an integrated circuit (IC) package including a first die at least partially embedded in a first encapsulation layer and a second die at least partially embedded in a second encapsulation layer. The first die may have a first plurality of die-level interconnect structures disposed at a first side of the first encapsulation layer. The IC package may also include a plurality of electrical routing features at least partially embedded in the first encapsulation layer and configured to route electrical signals between a first and second side of the first encapsulation layer. The second side may be disposed opposite to the first side. The second die may have a second plurality of die-level interconnect structures that may be electrically coupled with at least a subset of the plurality of electrical routing features by bonding wires.Type: GrantFiled: September 30, 2022Date of Patent: February 25, 2025Inventors: Thorsten Meyer, Pauli Jaervinen, Richard Patten
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Publication number: 20230023328Abstract: Embodiments of the present disclosure are directed towards an integrated circuit (IC) package including a first die at least partially embedded in a first encapsulation layer and a second die at least partially embedded in a second encapsulation layer. The first die may have a first plurality of die-level interconnect structures disposed at a first side of the first encapsulation layer. The IC package may also include a plurality of electrical routing features at least partially embedded in the first encapsulation layer and configured to route electrical signals between a first and second side of the first encapsulation layer. The second side may be disposed opposite to the first side. The second die may have a second plurality of die-level interconnect structures that may be electrically coupled with at least a subset of the plurality of electrical routing features by bonding wires.Type: ApplicationFiled: September 30, 2022Publication date: January 26, 2023Inventors: Thorsten Meyer, Pauli Jaervinen, Richard Patten
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Patent number: 10319688Abstract: An antenna is described on ceramics that may be used for a packaged die. In one example, a package has a die, a ceramic substrate over the die, an antenna attached to the ceramic substrate, and conductive leads electrically connecting the antenna to the die.Type: GrantFiled: December 9, 2013Date of Patent: June 11, 2019Assignee: Intel CorporationInventors: Andreas Wolter, Saravana Maruthamuthu, Mikael Knudsen, Thorsten Meyer, Georg Seidemann, Pablo Herrero, Pauli Jaervinen
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Patent number: 10249598Abstract: Embodiments of the present disclosure are directed towards an integrated circuit (IC) package including a first die at least partially embedded in a first encapsulation layer and a second die at least partially embedded in a second encapsulation layer. The first die may have a first plurality of die-level interconnect structures disposed at a first side of the first encapsulation layer. The IC package may also include a plurality of electrical routing features at least partially embedded in the first encapsulation layer and configured to route electrical signals between a first and second side of the first encapsulation layer. The second side may be disposed opposite to the first side. The second die may have a second plurality of die-level interconnect structures that may be electrically coupled with at least a subset of the plurality of electrical routing features by bonding wires.Type: GrantFiled: March 8, 2018Date of Patent: April 2, 2019Assignee: Intel CorporationInventors: Thorsten Meyer, Pauli Jaervinen, Richard Patten
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Publication number: 20180315737Abstract: Embodiments of the present disclosure are directed towards an integrated circuit (IC) package including a first die at least partially embedded in a first encapsulation layer and a second die at least partially embedded in a second encapsulation layer. The first die may have a first plurality of die-level interconnect structures disposed at a first side of the first encapsulation layer. The IC package may also include a plurality of electrical routing features at least partially embedded in the first encapsulation layer and configured to route electrical signals between a first and second side of the first encapsulation layer. The second side may be disposed opposite to the first side. The second die may have a second plurality of die-level interconnect structures that may be electrically coupled with at least a subset of the plurality of electrical routing features by bonding wires.Type: ApplicationFiled: July 6, 2018Publication date: November 1, 2018Inventors: Thorsten Meyer, Pauli Jaervinen, Richard Patten
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Publication number: 20180197840Abstract: Embodiments of the present disclosure are directed towards an integrated circuit (IC) package including a first die at least partially embedded in a first encapsulation layer and a second die at least partially embedded in a second encapsulation layer. The first die may have a first plurality of die-level interconnect structures disposed at a first side of the first encapsulation layer. The IC package may also include a plurality of electrical routing features at least partially embedded in the first encapsulation layer and configured to route electrical signals between a first and second side of the first encapsulation layer. The second side may be disposed opposite to the first side. The second die may have a second plurality of die-level interconnect structures that may be electrically coupled with at least a subset of the plurality of electrical routing features by bonding wires.Type: ApplicationFiled: March 8, 2018Publication date: July 12, 2018Inventors: Thorsten Meyer, Pauli Jaervinen, Richard Patten
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Patent number: 9972601Abstract: Embodiments of the present disclosure are directed towards an integrated circuit (IC) package including a first die at least partially embedded in a first encapsulation layer and a second die at least partially embedded in a second encapsulation layer. The first die may have a first plurality of die-level interconnect structures disposed at a first side of the first encapsulation layer. The IC package may also include a plurality of electrical routing features at least partially embedded in the first encapsulation layer and configured to route electrical signals between a first and second side of the first encapsulation layer. The second side may be disposed opposite to the first side. The second die may have a second plurality of die-level interconnect structures that may be electrically coupled with at least a subset of the plurality of electrical routing features by bonding wires.Type: GrantFiled: September 26, 2014Date of Patent: May 15, 2018Assignee: INTEL CORPORATIONInventors: Thorsten Meyer, Pauli Jaervinen, Richard Patten
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Patent number: 9819327Abstract: Techniques and configurations are disclosed for bulk acoustic wave resonator (BAWR) tuner circuits and their use in integrated circuit (IC) packages and mobile communication devices for radio frequency (RF) communication. In some embodiments, a mobile communication device may include an antenna; a transmitter circuit having an output port, a tuner circuit having one or more BAWRs, an antenna port coupled to the antenna, a transmitter port coupled to the output port of the transmitter circuit, and a control port; and a control circuit, coupled to the control port, configured to adjust an impedance of the tuner circuit, via adjustment of a BAWR or another component of the tuner circuit, based at least in part on an impedance of the antenna. Other embodiments may be described and/or claimed.Type: GrantFiled: June 26, 2013Date of Patent: November 14, 2017Assignee: INTEL IP CORPORATIONInventors: Saravana Maruthamuthu, Thorsten Meyer, Pablo Herrero, Andreas Wolter, Georg Seidemann, Mikael Knudsen, Pauli Jaervinen
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Publication number: 20160276311Abstract: Embodiments of the present disclosure are directed towards an integrated circuit (IC) package including a first die at least partially embedded in a first encapsulation layer and a second die at least partially embedded in a second encapsulation layer. The first die may have a first plurality of die-level interconnect structures disposed at a first side of the first encapsulation layer. The IC package may also include a plurality of electrical routing features at least partially embedded in the first encapsulation layer and configured to route electrical signals between a first and second side of the first encapsulation layer. The second side may be disposed opposite to the first side. The second die may have a second plurality of die-level interconnect structures that may be electrically coupled with at least a subset of the plurality of electrical routing features by bonding wires.Type: ApplicationFiled: August 26, 2014Publication date: September 22, 2016Applicant: INTEL CORPORATIONInventors: Thorsten Meyer, Pauli Jaervinen, Richard Patten
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Publication number: 20160240492Abstract: An antenna is described on ceramics that may be used for a packaged die. In one example, a package has a die, a ceramic substrate over the die, an antenna attached to the ceramic substrate, and conductive leads electrically connecting the antenna to the die.Type: ApplicationFiled: December 9, 2013Publication date: August 18, 2016Inventors: Andreas Wolter, Saravana Maruthamuthu, Mikael Knudsen, Meyer Thorsten, Georg Seidemann, Pablo Herrero, Pauli Jaervinen
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Publication number: 20150333401Abstract: Techniques and configurations are disclosed for bulk acoustic wave resonator (BAWR) tuner circuits and their use in integrated circuit (IC) packages and mobile communication devices for radio frequency (RF) communication. In some embodiments, a mobile communication device may include an antenna; a transmitter circuit having an output port, a tuner circuit having one or more BAWRs, an antenna port coupled to the antenna, a transmitter port coupled to the output port of the transmitter circuit, and a control port; and a control circuit, coupled to the control port, configured to adjust an impedance of the tuner circuit, via adjustment of a BAWR or another component of the tuner circuit, based at least in part on an impedance of the antenna. Other embodiments may be described and/or claimed.Type: ApplicationFiled: June 26, 2013Publication date: November 19, 2015Inventors: Saravana MARUTHAMUTHU, Thorsten MEYER, Pablo HERRERO, Andreas WOLTER, Georg SEIDEMANN, Mikael KNUDSEN, Pauli JAERVINEN
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Patent number: 8779564Abstract: A semiconductor device may include: a chip; a chip packaging structure at least partially surrounding the chip and having a receiving region configured to receive a first capacitive coupling structure; a first capacitive coupling structure disposed in the receiving region; and a second capacitive coupling structure disposed over the first capacitive coupling structure and capacitively coupled to the first capacitive coupling structure.Type: GrantFiled: March 14, 2013Date of Patent: July 15, 2014Assignee: Intel IP CorporationInventors: Mikael Knudsen, Thorsten Meyer, Saravana Maruthamuthu, Andreas Wolter, Georg Seidemann, Pablo Herrero, Pauli Jaervinen