Abstract: A method to speed up the training of the output frequency signal (Out) of a frequency synthesizer circuit. The circuit comprises a voltage controlled oscillator (7) controlled by a filtered (6) feedback signal (Fb) output by a phase detector circuit (5) having a first input signal (Rs), which is produced by a reference counter (3) dividing an external reference signal produced by a reference oscillator (2), and a second input signal (Cs) produced by a programmable counter (4) dividing an output signal (Vs) from the voltage controlled oscillator (7). When the training process is started, the internal reference frequency of the first and second input signals (Rs, Cs) is simultaneously increased by a predetermined amount for a predetermined time.