Abstract: A method and electronic circuit for changing the gain of a radio frequency signal. The apparatus is an electronic circuit comprising one or more variable gain electronic elements, and one or more adjustable phase shifting elements. The method comprises the steps of receiving a radio frequency signal, varying the gain of the variable gain electronic element while the variable gain electronic element changes the amplitude of the radio frequency signal, and adjusting an adjustable phase shifting element to generate a reverse phase shift in the radio frequency signal in response to the associated phase shift from the step of varying the gain.

Abstract: A method and electronic circuit for changing the gain of a radio frequency signal. The apparatus is an electronic circuit comprising one or more variable gain electronic elements, and one or more adjustable phase shifting elements. The method comprises the steps of receiving a radio frequency signal, varying the gain of the variable gain electronic element while the variable gain electronic element changes the amplitude of the radio frequency signal, and adjusting an adjustable phase shifting element to generate a reverse phase shift in the radio frequency signal in response to the associated phase shift from the step of varying the gain.

Abstract: A method and apparatus for modulating a beam from a laser with an electro-absorption modulator, and determining the optical power of the beam by measuring a back current produced by the electro-absorption modulator. The apparatus comprises an electro-absorption modulator and a back current detector. The electro-absorption modulator receives an electronic digital signal from an electro-absorption driver. The electro-absorption modulator modulates the beam of the laser according to the electronic digital signal. While modulating the beam, the electro-absorption modulator produces a back current. This back current is proportional to the optical power of the beam. The back current detector measures the back current to determine the optical power of the beam.

Abstract: A method and electronic circuit for changing the gain of a radio frequency signal. The apparatus is an electronic circuit comprising one or more variable gain electronic elements, and one or more adjustable phase shifting elements. The method comprises the steps of receiving a radio frequency signal, varying the gain of the variable gain electronic element while the variable gain electronic element changes the amplitude of the radio frequency signal, and adjusting an adjustable phase shifting element to generate a reverse phase shift in the radio frequency signal in response to the associated phase shift from the step of varying the gain.

Abstract: A method and electronic circuit for changing the gain of a radio frequency signal. The apparatus is an electronic circuit comprising one or more variable gain electronic elements, and one or more adjustable phase shifting elements. The method comprises the steps of receiving a radio frequency signal, varying the gain of the variable gain electronic element while the variable gain electronic element changes the amplitude of the radio frequency signal, and adjusting an adjustable phase shifting element to generate a reverse phase shift in the radio frequency signal in response to the associated phase shift from the step of varying the gain.

Abstract: A method and apparatus for modulating a beam from a laser with an electro-absorption modulator, and determining the optical power of the beam by measuring a back current produced by the electro-absorption modulator. The apparatus comprises an electro-absorption modulator and a back current detector. The electro-absorption modulator receives an electronic digital signal from an electro-absorption driver. The electro-absorption modulator modulates the beam of the laser according to the electronic digital signal. While modulating the beam, the electro-absorption modulator produces a back current. This back current is proportional to the optical power of the beam. The back current detector measures the back current to determine the optical power of the beam.

Abstract: To protect victim bondwires in a packaged electronic component from crosstalk induced by noisy aggressor bondwires, shielding bondwires are configured between the victim bondwires and the aggressor bondwires. The shielding bondwires, on either side of the victim bondwires, are connected to the same reference voltage on the package side of the component and to each other on the die side of the component, e.g., via a metal connection mounted on the die. As configured in one embodiment, the shielding bondwires and metal connection form a two-dimensional Faraday cage that shields the victim bondwires from crosstalk induced by the aggressor bondwires.

Abstract: In one embodiment, an integrated circuit (e.g., FPGA) has two voltage regulators sharing stability and filter capacitors. A switch is located between each plate of each capacitor and a common voltage reference (e.g., ground) such that one of the two voltage regulators can be selectively connected to ground via the stability and filter capacitors.

Abstract: In one embodiment, multiple (serializer-deserializer) SERDES channels are aligned by selectively slipping one or more of the incoming serial data streams one bit at a time prior to deserialization. Within each SERDES channel, a slip circuit slips the corresponding serial data stream by one bit (i.e., one unit interval (UI)) by extending the high portion of the duty cycle of a corresponding clock signal. The high portion of the clock signal is extended using a 3-to-1 mux that selects a fixed high signal, such as the high power supply rail, as an intermediate mux output signal whenever transitioning between two different applied clock signals that are offset from one another by one UI. In this way, the slip circuit avoids glitches that might otherwise result from switching directly between the two clock signals.

Abstract: In one embodiment, multiple (serializer/deserializer) SERDES channels are aligned by selectively slipping one or more of the incoming serial data streams one bit at a time prior to deserialization. Within each SERDES channel, a slip circuit slips the corresponding serial data stream by one bit (i.e., one unit interval (UI)) by extending the high portion of the duty cycle of a corresponding clock signal. The high portion of the clock signal is extended using a 3-to-1 mux that selects a fixed high signal, such as the high power supply rail, as an intermediate mux output signal whenever transitioning between two different applied clock signals that are offset from one another by one UI. In this way, the slip circuit avoids glitches that might otherwise result from switching directly between the two clock signals.

Abstract: In one embodiment, a combined VGA-and-equalizer (VGA-EQ) circuit for a communication link includes a current-mode logic (“CML”) amplifier with an inductive load circuit. The CML amplifier has a gain control terminal and is operable to amplify, with an adjustable gain, a signal received at an input terminal and provide the amplified signal at an output terminal. The CML amplifier has a first gain at frequencies below a predetermined frequency value and a second gain at frequencies in a predetermined frequency range above the predetermined frequency value, wherein the second gain is higher than the first gain. The higher second gain of the VGA-EQ circuit causes a reduction in inter-symbol interference in a signal received by the receiver.

Abstract: In an exemplary decision-feedback equalizer (DFE) of a serializer/deserializer (SerDes) receiver, a single current mirror array is shared by multiple current digital-to-analog converter (IDAC) functions. The DFE has an initial amplifier stage that applies an initial coefficient COEFF0 to an input data signal and a number of (e.g., five) additional amplifier stages that apply additional coefficients (e.g., COEFF1-COEFF5) to different delayed versions of the recovered output data stream. The outputs of the initial and multiple additional amplifier stages are summed to generate an equalized data signal that is applied to a clock-and-data recovery (CDR) circuit. Due to certain characteristics of the equalizer function, the multiple additional amplifier stages can be implemented using a single shared current mirror array, which save significant amounts of chip area compared to conventional implementations in which each additional amplifier stage has its own dedicated current mirror array.

Abstract: An AC-coupled differential drive circuit for an optical modulator is utilized, where a common “node” is defined between top (or bottom) plates of the modulator arms themselves (the “arms” of a modulator taking the form of MOS capacitors). A low pass filter is disposed between the differential driver output and the modulator's common node to provide the desired AC coupling by filtering out the DC bias voltage of the driver circuit itself without the need for a separate, external AC coupling capacitor. An independent, adjustable DC potential can then be applied to the common node, and will appear in a balanced manner across each arm of the modulator to provide the desired DC bias for the modulator independent of the DC bias of the driver circuit.

Abstract: An optical modulator is formed to include an adjustable drive arrangement for dynamically adjusting the effective length of the optical signals path(s) within the modulator. Each modulator arm is partitioned into a plurality of segments, with each segment coupled to a separate electrical signal driver. Therefore, the effective length of each modulator arm will be a function of the number of drivers that are activated for each arm at any given point in time. A feedback arrangement may be used with the plurality of drivers to dynamically adjust the operation of the modulator by measuring the extinction ratio as a function of optical power, turning “on” or “off” individual drivers accordingly.

Abstract: Computer-aided design (CAD) tools are used to perform the integrated design, verification and layout of electrical and optical components in a monolithic, silicon-based electro-optic chip. Separate top-level behavioral logic designs are prepared for the three different types of elements included within the final, silicon-based monolithic structure: (1) digital electronic integrated circuit elements; (2) analog/mixed signal electronic integrated circuit elements; and (3) opto-electronic elements (including passive and active optical elements). Once the behavioral logic design is completed, the results are combined and co-simulated. A physical layout design is developed and verified for each different type of element in the circuit. The separate physical layouts are then co-verified, to assess the properties of the overall physical design.

Abstract: Computer-aided design (CAD) tools are used to perform the integrated design, verification and layout of electrical and optical components in a monolithic, silicon-based electro-optic chip. Separate top-level behavioral logic designs are prepared for the three different types of elements included within the final, silicon-based monolithic structure: (1) digital electronic integrated circuit elements; (2) analog/mixed signal electronic integrated circuit elements; and (3) opto-electronic elements (including passive and active optical elements). Once the behavioral logic design is completed, the results are combined and co-simulated. A physical layout design is developed and verified for each different type of element in the circuit. The separate physical layouts are then co-verified, to assess the properties of the overall physical design.