Abstract: A digital phase acquisition clock recovery circuit includes a digital phase-locked loop that employs a truth table decoder to set the actual delay through a plurality of individual delay elements to generate a plurality of clock phase signals approximately equally spaced in time over one reference clock cycle, and a data sampler circuit that generates a plurality of received data samples from an incoming data sample taken at the rising edge of the respective clock phase signals and synchronizes the data samples to reference clock on a bit period-by-bit period basis. A digital phase acquisition circuit includes an edge detector which evaluates the data samples over each bit period to detect the location of a transition between respective adjacent samples, wherein logic is employed to continually determine the "relative quality" of each data sample, based upon its sampling time being furthest from a detected edge transition.

Abstract: A re-enterable environmentally sealed enclosure for housing circuitry and/or cable components of a communication network employs a removable cover attached to an enclosure base by a pivoting cam-tracking system. The tracking configuration positions the cover in a manner that, as it approaches the enclosure base when being closed, a seal located in the cover is evenly compressed along its entire perimeter against a corresponding mating surface on the base, thereby distributing the compressive force equally across the entire seal, with any shear forces substantially eliminated. A single tensioning system is provided adjacent the cam-tracking system, so that the tracking system does not operate as a counter-lever to the tensioning system, and visa versa, thereby improving the distribution of force across the seal.

Abstract: An intregal cable retention and sealing apparatus has reusable clamping mechanisms for the entry and exit of a wide variety of cable types and sizes to a sealed enclosure. The device is formed by "mirror-image" body halves having, when assembled, at least one axial passageway formed therethrough to accomodate one or more respective cables. One end of the apparatus includes a chamber for housing a sealing medium, whereas the other end includes a cable retention mechanism.

Abstract: A coupler verification test circuit includes first and second circuits one of which is disposed at a head end of an optical fiber network and the other of which is disposed at a subscriber interface unit to be attached to the network when the head end is not operational. The subscriber interface circuit transmits instructions to a transceiver board in the subscriber interface unit for transmission to the network head end whereat the circuit thereat generates either no return signal, an acknowledgment return signal, or a default return signal. The test circuit at the subscriber interface unit then analyzes the return signal and visually indicates to a craftsman whether or not the transceiver board and other components of the SIU are operating correctly, e.g. whether or not the acknowledgement signal was returned and detected.

Abstract: A digital phase acquisition circuit includes logic for detecting an edge of incoming data and a plurality of candidate clock phases, the circuitry further including logic for determining when the data undergoes a phase transition and at least one candidate phase which undergoes a digitally equivalent transition close in time to the data transition so as to enable the candidate phase to be used for a clock for recovering information representative of the data. The circuit allows clock to be recovered within 1 bit time of a predetermined data transition occurring, thus allowing preambles of 1 bit to be utilized in data packets.

Abstract: A digital phase acquisition circuit includes circuits for detecting an edge of incoming data and a plurality of candidate clock phases, the circuitry further including logic for determining when the data undergoes a predetermined phase transition and at least one candidate phase which undergoes a digitally equivalent transition close in time to the data transition so as to enable the candidate phase to be used for choosing an appropriate clock phase for recovering information representative of the data. The circuit further includes logic for comparing a frequency of the chosen clock pulse and the data and adjusting at least one of these frequencies when a predetermined amount of drift therebetween is detected. The invention allows clock to be recovered within 1 bit time of a predetermined data transition occurring and allows an appropriate clock to be maintained through an entire packet regardless of packet length.