Abstract: A method is provided for generation of a circuit design. A plurality of components, including at least a processor and a peripheral device, is instantiated in a circuit design. One or more parameterizable data bus interface blocks are automatically selected based on the master-slave relationships, requirements, and capabilities of the components. The one or more parameterizable data bus interface blocks are instantiated in the circuit design. In response to user input, values are assigned to one or more parameters of the processor. The plurality of components and data bus interface blocks are automatically parameterized by determining appropriate parameter values according to the parameters of the processor and capabilities and requirements of the components and data bus interface blocks.

Abstract: Decoding an address in an address space including a plurality of local ranges and a plurality of peripheral ranges is described. Various approaches for decoding an input address include determining decoder address bits of the address space that distinguish local ranges from each other and that distinguish local ranges from peripheral ranges. The local and peripheral ranges are interleaved and have a plurality of sizes. The number of decoder address bits is less than the number of address bits in the address space and less than the number of local ranges plus the number of peripheral ranges. Using the decoder address bits of an input address, it is determined whether the input address is within a portion of the address space that includes one of the local ranges and does not include any of the peripheral ranges nor the local ranges other than the one of the local ranges.

Abstract: Various approaches for generating a clock accurate simulation model from a circuit design description are disclosed. In one approach, a graph representation of the circuit design description is created. The graph representation includes nodes and edges. From the nodes in the graph representation, a plurality of register nodes are generated to correspond to respective register functions. Logic optimization is performed on nodes that represent combinational logic functions. For each register node and each output node, an evaluation equation is generated after performing logic optimization. For each clock cycle of a logic simulation, each evaluation equation is evaluated and produces an output value for the next clock cycle.