Abstract: A circuit comprising: an input terminal configured to receive an input-signal; an output terminal configured to provide an output-signal; a reference circuit comprising: a first output terminal configured to provide a first-reference-signal; a second output terminal configured to provide a second-reference-signal; and a third output terminal configured to provide a third-reference-signal. A comparator-block configured to compare a comparator-input-voltage-signal representative of signalling received at the input terminal with: (i) the first-reference-signal, (ii) the second-reference-signal and (iii) the third-reference-signal in order to generate a comparison-signal. A control-block configured to set the output-signal as one of at least two voltage levels based on the comparison-signal; and an input-control-circuit configured to apply a feedback-control-signal to the input-terminal based on the comparison-signal.

Abstract: A loop-filter comprising: a first-integrator, and one or more further-integrators. The first-integrator is an active-RC integrator, and comprises a first-integrator-input-terminal configured to receive: (i) an input-signal, and (ii) a feedback-signal; a first-integrator-first-output-terminal configured to provide a first-integrator-first-output-signal; and one or more first-integrator-further-output-terminals. Each of the one or more further-integrators is a Gm-C integrator, and they are connected in series between the first-integrator-first-output-terminal and a loop-filter-output-terminal. For a first further-integrator in the series, the further-integrator-input-terminal is configured to receive the first-integrator-first-output-signal. For any subsequent further-integrators in the series, the further-integrator-input-terminal is configured to receive: (i) the further-integrator-output-signal from the preceding further-integrator in the series; and (ii) one of the first-integrator-further-output-signals.

Abstract: A loop-filter comprising: a first-integrator, and one or more further-integrators. The first-integrator is an active-RC integrator, and comprises a first-integrator-input-terminal configured to receive: (i) an input-signal, and (ii) a feedback-signal; a first-integrator-first-output-terminal configured to provide a first-integrator-first-output-signal; and one or more first-integrator-further-output-terminals. Each of the one or more further-integrators is a Gm-C integrator, and they are connected in series between the first-integrator-first-output-terminal and a loop-filter-output-terminal. For a first further-integrator in the series, the further-integrator-input-terminal is configured to receive the first-integrator-first-output-signal. For any subsequent further-integrators in the series, the further-integrator-input-terminal is configured to receive: (i) the further-integrator-output-signal from the preceding further-integrator in the series; and (ii) one of the first-integrator-further-output-signals.

Abstract: A circuit comprising: an input terminal configured to receive an input-signal; an output terminal configured to provide an output-signal; a reference circuit comprising: a first output terminal configured to provide a first-reference-signal; a second output terminal configured to provide a second-reference-signal; and a third output terminal configured to provide a third-reference-signal. A comparator-block configured to compare a comparator-input-voltage-signal representative of signalling received at the input terminal with: (i) the first-reference-signal, (ii) the second-reference-signal and (iii) the third-reference-signal in order to generate a comparison-signal. A control-block configured to set the output-signal as one of at least two voltage levels based on the comparison-signal; and an input-control-circuit configured to apply a feedback-control-signal to the input-terminal based on the comparison-signal.

Abstract: In High Voltage CMOS technologies the supply voltage is typically higher than the maximum allowed gate voltage. In a switching output stage of amplifiers such class-D amplifiers and DC-DC converters the gates of the power field effect transistors need to be charged quickly. This requires a gate driver that is capable of delivering large currents without exceeding the maximum allowed voltage on the gate of the power field effect transistors.

Abstract: In High Voltage CMOS technologies the supply voltage is typically higher than the maximum allowed gate voltage. In a switching output stage of amplifiers such class-D amplifiers and DC-DC converters the gates of the power field effect transistors need to be charged quickly. This requires a gate driver that is capable of delivering large currents without exceeding the maximum allowed voltage on the gate of the power field effect transistors.

Abstract: An electronic device with an amplifier output stage (OS) and an over-current detection means (OCDM) for detecting an output over-current (IHS, ILS) of the output stage (OS) is provided. The over-current detection means (OCDM) comprises a level detection means (LDM) for detecting a level of the output current (IO) exceeding a first level of the output current (IDET), and a timing detection means (TDM) for detecting a duration during which the output current (IO) exceeds the first current level (IDET) being a maximum current level.

Abstract: In a signal processing arrangement, a digital-to-analog converter (DAC1) of the finite impulse response type converts a serial bitstream (BSL) into an analog output signal (AL). The digital-to-analog converter (DAC1) comprises at least two current source arrays (CCA1, CC A2). In a first current source array (CCA1), a current definition cell (CD1) generates a first basic current, and a plurality of first current copy cells ( . . . , CC40, CC41, . . . ) provide respective scaled copies of the first basic current to constitute first filter coefficient currents ( . . . , IP40, IP41, . . . ). In a further current source array (CCA2), a further current definition cell (CD2) generates a further basic current, and a plurality of current further copy cells (CC1, CC2, . . . , CC80) provide respective scaled copies of the further basic current to constitute further filter coefficient currents (IP1, IP2, . . . , IP80).

Abstract: The present invention relates to a frequency-independent voltage divider in which a compensation structure (10) for compensating a distributed parasitic capacitance of a resistor arrangement (20) is arranged between the resistor arrangement (20) and a substrate (50). Thereby, the compensation structure (10) shields the resistor arrangement (20) partly from the substrate (50), and thus shields the parasitic capacitance. This allows for an improved compensation.

Abstract: In a signal processing arrangement, a digital-to-analog converter (DAC1) of the finite impulse response type converts a serial bitstream (BSL) into an analog output signal (AL). The digital-to-analog converter (DAC1) comprises at least two current source arrays (CCA1, CC A2). In a first current source array (CCA1), a current definition cell (CD1) generates a first basic current, and a plurality of first current copy cells ( . . . , CC40, CC41, . . . ) provide respective scaled copies of the first basic current to constitute first filter coefficient currents ( . . . , IP40, IP41, . . . ). In a further current source array (CCA2), a further current definition cell (CD2) generates a further basic current, and a plurality of current further copy cells (CC1, CC2, . . . , CC80) provide respective scaled copies of the further basic current to constitute further filter coefficient currents (IP1, IP2, . . . , IP80).

Abstract: An electronic device with an amplifier output stage (OS) and an over-current detection means (OCDM) for detecting an output over-current (IHS, ILS) of the output stage (OS) is provided. The over-current detection means (OCDM) comprises a level detection means (LDM) for detecting a level of the output current (10) exceeding a first level of the output current (IDET), and a timing detection means (TDM) for detecting a duration during which the output current (10) exceeds the first current level (IDET) being a maximum current level.

Abstract: An electronic circuit comprising an amplifier includes an output terminal (OUT) for supplying an output signal (Vout) to a load, the amplifier comprising an output transistor (N2, P1) having a first main terminal coupled to a supply voltage terminal (VSS, VDD) of the amplifier, a second main terminal coupled to the output terminal (OUT), and a control terminal. In order to avoid that the output transistor (N2, P1) can enter its linear state which would cause the amplifier to act unacceptably slow for some purposes, the electronic circuit further comprises a controller adapted to prevent the output transistor (N2, P1) to enter its linear state whereby the controller is arranged for reducing a control voltage (Vcntrl) between the control terminal and the first main terminal when an output voltage (Vout) between the second main terminal and the first main terminal is below a defined level.

Abstract: An electronic circuit comprising an amplifier comprising an output terminal (OUT) for supplying an output signal (Vout) to a load, the amplifier comprising an output transistor (N2, P1) having a first main terminal coupled to a supply voltage terminal (Vss, VDD) of the amplifier, a second main terminal coupled to the output terminal (OUT), and a control terminal. In order to avoid that the output transistor (N2, P1) can enter its linear state which would cause the amplifier to act unacceptably slow for some purposes, the electronic circuit further comprises control means for avoiding the output transistor (N2, P1) to enter its linear state whereby the control means are arranged for reducing a control voltage (Vcntrl) between the control terminal and the first main terminal when an output voltage (Vout) between the second main terminal and the first main terminal is below a defined level.