Abstract: A translation lookaside buffer (TLB) is disclosed formed using RAM and synthesisable logic circuits. The TLB provides logic within the synthesisable logic for pairing down a number of memory locations that must be searched to find a translation to a physical address from a received virtual address. The logic provides a hashing circuit for hashing the received virtual address and uses the hashed virtual address to index the RAM to locate a line within the RAM that provides the translation.

Abstract: A translation lookaside buffer (TLB) is disclosed formed using RAM and synthesisable logic circuits. The TLB provides logic within the synthesisable logic for pairing down a number of memory locations that must be searched to find a translation to a physical address from a received virtual address. The logic provides a hashing circuit for hashing the received virtual address and uses the hashed virtual address to index the RAM to locate a line within the RAM that provides the translation.

Abstract: The present invention relates to a data processing system comprising a first interrupt controller with an interrupt source interface, an interrupt controller interface, prioritizing means, and an interrupt controller output. The Data processing system further comprises a processing unit providing an interrupt controller interface. The invention also is related to a method for handling interrupt requests. Accordingly, interrupt requests generated by a first plurality of interrupt sources, a second selected interrupt request, a second priority signal, and a second interrupt source index signal generated by a second interrupt controller are received by the first interrupt controller Among said plurality of interrupt requests and said second selected interrupt request a first single interrupt request is selected and transmitted along with a first priority signal, and a first index signal to the processing unit; which initiates an appropriate interrupt service routine on the basis of said first index signal.

Abstract: A translation lookaside buffer (TLB) is disclosed formed using RAM and synthesisable logic circuits. The TLB provides logic within the synthesisable logic for pairing down a number of memory locations that must be searched to find a translation to a physical address from a received virtual address. The logic provides a hashing circuit for hashing the received virtual address and uses the hashed virtual address to index the RAM to locate a line within the RAM that provides the translation.