Abstract: A phase lock circuit comprising a phase frequency comparator having a first input for a reference signal and a second input for a feedback signal, as well as outputs for furnishing an up-signal or a down-signal to a control charge pump circuit, which control charge pump circuit is connected with the outputs of the phase frequency comparator and has an output which is connected via a loop filter with a voltage-controlled oscillator provided with tuning means, the output of the oscillator being connected via a frequency divider with the second input of the phase frequency comparator, while for furnishing a tuning voltage for the tuning means a voltage charge pump circuit is provided, which is combined with the control charge pump circuit to form a combined charge pump circuit connected with the output of the phase frequency comparator.

Abstract: Several embodiments of an intermediate frequency (IF) amplifier, which exhibit improved distortion characteristics, are disclosed for use in an integrated transceiver circuit. The amplifier has a differential stage comprising two transistors which compare a voltage derived from an amplifier input signal with a voltage derived from the amplifier output signal to determine the portion of a bias current which will be supplied to one or more current mirrors. Output current from the one or more current mirrors is further used to bias an output transistor which drives a load impedance.

Abstract: An image reject circuit comprises a local oscillator 26 for producing a local oscillator signal. A tunable phase shifting network 29 has inputs 1, 3 for receiving the local oscillator signal and producing an output in-phase (I) signal 13, 25 and an output quadrature (Q) signal 15, 27. A first amplitude detector 33 determines the amplitude of the output I signal, while a second amplitude detector 35 determines the amplitude of the output Q signal. A comparator 37 determines the difference between the amplitudes of the output I and Q signals, to produce a tuning signal for tuning the phase shifting network 29 to bring the difference between the amplitudes of the output I and Q signals towards a desired level. Preferably, the tunable phase shifting network 29 (shown in FIG. 4) comprises a combination of tunable capacitive, resistive and inductive elements.

Abstract: A phase lock circuit comprising a phase frequency comparator having a first input for a reference signal and a second input for a feedback signal, as well as outputs for furnishing an up-signal or a down-signal to a control charge pump circuit, which control charge pump circuit is connected with the outputs of the phase frequency comparator and has an output which is connected via a loop filter with a voltage-controlled oscillator provided with tuning means, the output of the oscillator being connected via a frequency divider with the second input of the phase frequency comparator, while for furnishing a tuning voltage for the tuning means a voltage charge pump circuit is provided, which is combined with the control charge pump circuit to form a combined charge pump circuit connected with the output of the phase frequency comparator.

Abstract: A method and a device of sampling an analog signal (U(t)) by obtaining first sequences of discrete sample values (SI1(t), SQ1(t)) of In-phase (I) and Quadrature-phase (Q) components (Ui(t), UQ(t)) of the analog signall (U(t)) and second sequences of discrete sample values (SI2(t), SQ2(t)) of the I and Q components (Ui(t), UQ(t)), by sampling of the I and Q components with sampling sequences (&phgr;1(t), &phgr;2(t)) having equal sampling rate (&ohgr;s) and a mutual phase shift of 90° relative to their sampling rate period (T). The sample values of the I component of the first sequence (SI1(t)) and the sample values of the Q component of the second sequence (SQ2(t)) are summed (9) to form a third sequence of sample values S3(t). The sample values of the Q component of the first sequence (SQ1(t)) and the sample values of the I component of the second sequence SI2(t)) are summed (10) to form a fourth sequence of sample values (S4(t)).