Patents by Inventor Paulus Z. A. van der Putte

Paulus Z. A. van der Putte has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Self-aligned metallization for semiconductor device and process using selectively deposited tungsten
    Patent number: 4937657
    Abstract: A self-aligned metallization for an MOS device is described in which a first layer of tungsten is selectively deposited on the exposed silicon surfaces of the device including at least the source, drain and gate regions of the device, a layer of material providing nucleation sites for tungsten is selectively formed across insulating oxide regions of the device, and a second tungsten layer is selectively deposited on the nucleating layer and the exposed first tungsten layer to provide interconnection across the oxide regions. In addition to having a low electrical resistivity, such a metallization enables relaxed mask alignment and etching tolerance requirements, and is therefore useful in VLSI circuits.
    Type: Grant
    Filed: December 8, 1988
    Date of Patent: June 26, 1990
    Assignee: Signetics Corporation
    Inventors: Janet M. DeBlasi, Paulus Z. A. Van Der Putte
  • Self-aligned metallization for semiconductor device and process using selectively deposited tungsten
    Patent number: 4822749
    Abstract: A self-aligned metallization for an MOS device is described in which a first layer of tungsten is selectively deposited on the exposed silicon surfaces of the device including at least the source, drain and gate regions of the device, a layer of material providing nucleation sites for tungsten is selectively formed across insulating oxide regions of the device, and a second tungsten layer is selectively deposited on the nucleating layer and the exposed first tungsten layer to provide interconnection across the oxide regions. In addition to having a low electrical resistivity, such a metallization enables relaxed mask alignment and etching tolerance requirements, and is therefore useful in VLSI circuits.
    Type: Grant
    Filed: August 27, 1987
    Date of Patent: April 18, 1989
    Assignee: North American Philips Corporation, Signetics Division
    Inventors: Janet M. Flanner, Paulus Z. A. van der Putte