Abstract: Systems, methods, and apparatus for regenerating a data signal and a clock signal are provided. One of the apparatuses include clock regeneration loop circuitry configured to receive an input data signal transmitted without a reference clock signal, and to generate an output reference clock signal having an adjustable clock frequency that substantially matches a data rate of the input data signal; data detection loop circuitry configured to generate a phase offset control signal for adjusting a phase of a clock signal that samples the input data signal, and to generate, based on the phase offset control signal, a sampled input data signal; and an elastic buffer configured to generate, based on the output reference clock signal and the sampled input data signal, an output data signal that substantially aligns with the output reference clock signal, and enable the different adaptation dynamic of the loops.

Abstract: A continuous-time equalizer includes a first transconductance circuit to set a gain of an amplified signal in a link and a second transconductance circuit to set a zero frequency in a transfer function of the equalizer. The zero frequency controls a frequency range of the signal amplified in the link based on the gain set by the first transconductance circuit.