Abstract: Provided is a method of performing an internal processing operation of a memory device in a system including a host device and the memory device. The memory device includes a memory cell array and a processor-in-memory (PIM) performing an internal processing operation. In an internal processing mode, by the PIM, the memory device performs the internal processing operation based on internal processing information stored in the memory cell array. When the internal processing information is an internal processing operation command indicating a type of the internal processing operation, the memory device outputs the internal processing operation command including an internal processing read command and an internal processing write command to the host device. The host device issues to the memory device a priority command determined from among a data transaction command and the internal processing operation command.

Abstract: Provided is a method of performing an internal processing operation of a memory device in a system including a host device and the memory device. The memory device includes a memory cell array and a processor-in-memory (PIM) performing an internal processing operation. In an internal processing mode, by the PIM, the memory device performs the internal processing operation based on internal processing information stored in the memory cell array. When the internal processing information is an internal processing operation command indicating a type of the internal processing operation, the memory device outputs the internal processing operation command including an internal processing read command and an internal processing write command to the host device. The host device issues to the memory device a priority command determined from among a data transaction command and the internal processing operation command.

Abstract: Provided is a method of performing an internal processing operation of a memory device in a system including a host device and the memory device. The memory device includes a memory cell array and a processor-in-memory (PIM) performing an internal processing operation. In an internal processing mode, by the PIM, the memory device performs the internal processing operation based on internal processing information stored in the memory cell array. When the internal processing information is an internal processing operation command indicating a type of the internal processing operation, the memory device outputs the internal processing operation command including an internal processing read command and an internal processing write command to the host device. The host device issues to the memory device a priority command determined from among a data transaction command and the internal processing operation command.

Abstract: A timing-calibration circuit uses an active phase interpolator to calibrate clock delays through a number of passive fractional delay elements. The timing-calibration circuit minimizes system-wide power consumption by limiting the number and usage of active phase interpolators for delay adjustment in favor of the passive fractional delay elements.

Abstract: Provided is a method of performing an internal processing operation of a memory device in a system including a host device and the memory device. The memory device includes a memory cell array and a processor-in-memory (PIM) performing an internal processing operation. In an internal processing mode, by the PIM, the memory device performs the internal processing operation based on internal processing information stored in the memory cell array. When the internal processing information is an internal processing operation command indicating a type of the internal processing operation, the memory device outputs the internal processing operation command including an internal processing read command and an internal processing write command to the host device. The host device issues to the memory device a priority command determined from among a data transaction command and the internal processing operation command.

Abstract: Provided is a method of performing an internal processing operation of a memory device in a system including a host device and the memory device. The memory device includes a memory cell array and a processor-in-memory (PIM) performing an internal processing operation. In an internal processing mode, by the PIM, the memory device performs the internal processing operation based on internal processing information stored in the memory cell array. When the internal processing information is an internal processing operation command indicating a type of the internal processing operation, the memory device outputs the internal processing operation command including an internal processing read command and an internal processing write command to the host device. The host device issues to the memory device a priority command determined from among a data transaction command and the internal processing operation command.

Abstract: Provided is a method of performing an internal processing operation of a memory device in a system including a host device and the memory device. The memory device includes a memory cell array and a processor-in-memory (PIM) performing an internal processing operation. In an internal processing mode, by the PIM, the memory device performs the internal processing operation based on internal processing information stored in the memory cell array. When the internal processing information is an internal processing operation command indicating a type of the internal processing operation, the memory device outputs the internal processing operation command including an internal processing read command and an internal processing write command to the host device. The host device issues to the memory device a priority command determined from among a data transaction command and the internal processing operation command.

Abstract: Provided is a method of performing an internal processing operation of a memory device in a system including a host device and the memory device. The memory device includes a memory cell array and a processor-in-memory (PIM) performing an internal processing operation. In an internal processing mode, by the PIM, the memory device performs the internal processing operation based on internal processing information stored in the memory cell array. When the internal processing information is an internal processing operation command indicating a type of the internal processing operation, the memory device outputs the internal processing operation command including an internal processing read command and an internal processing write command to the host device. The host device issues to the memory device a priority command determined from among a data transaction command and the internal processing operation command.

Abstract: A stacked memory includes a logic semiconductor die, a plurality of memory semiconductor dies stacked with the logic semiconductor die, a plurality of through-silicon vias (TSVs) electrically connecting the logic semiconductor die and the memory semiconductor dies, a global processor disposed in the logic semiconductor die and configured to perform a global sub process corresponding to a portion of a data process, a plurality of local processors respectively disposed in the memory semiconductor dies and configured to perform local sub processes corresponding to other portions of the data process and a plurality of memory integrated circuits respectively disposed in the memory semiconductor dies and configured to store data associated with the data process.

Abstract: Provided is a method of performing an internal processing operation of a memory device in a system including a host device and the memory device. The memory device includes a memory cell array and a processor-in-memory (PIM) performing an internal processing operation. In an internal processing mode, by the PIM, the memory device performs the internal processing operation based on internal processing information stored in the memory cell array. When the internal processing information is an internal processing operation command indicating a type of the internal processing operation, the memory device outputs the internal processing operation command including an internal processing read command and an internal processing write command to the host device. The host device issues to the memory device a priority command determined from among a data transaction command and the internal processing operation command.

Abstract: A memory device includes a memory cell array having a plurality of memory cell groups with a corresponding plurality of independent channels, and the device and an operating method thereof perform an internal data processing operation for the memory cell groups. The memory device includes an internal command generator configured to generate one or more internal commands in order to perform an internal data processing operation in response to a reception of a command, and an internal common bus for a common internal processing channel which is disposed to be shared by the plurality of memory cell groups and configured to form a transmission path of data between the plurality of memory cell groups when the internal data processing operation is performed.

Abstract: A stacked memory includes a logic semiconductor die, a plurality of memory semiconductor dies stacked with the logic semiconductor die, a plurality of through-silicon vias (TSVs) electrically connecting the logic semiconductor die and the memory semiconductor dies, a global processor disposed in the logic semiconductor die and configured to perform a global sub process corresponding to a portion of a data process, a plurality of local processors respectively disposed in the memory semiconductor dies and configured to perform local sub processes corresponding to other portions of the data process and a plurality of memory integrated circuits respectively disposed in the memory semiconductor dies and configured to store data associated with the data process.

Abstract: A memory device includes a memory cell array having a plurality of memory cell groups with a corresponding plurality of independent channels, and the device and an operating method thereof perform an internal data processing operation for the memory cell groups. The memory device includes an internal command generator configured to generate one or more internal commands in order to perform an internal data processing operation in response to a reception of a command, and an internal common bus for a common internal processing channel which is disposed to be shared by the plurality of memory cell groups and configured to form a transmission path of data between the plurality of memory cell groups when the internal data processing operation is performed.

Abstract: A stacked memory includes a logic semiconductor die, a plurality of memory semiconductor dies stacked with the logic semiconductor die, a plurality of through-silicon vias (TSVs) electrically connecting the logic semiconductor die and the memory semiconductor dies, a global processor disposed in the logic semiconductor die and configured to perform a global sub process corresponding to a portion of a data process, a plurality of local processors respectively disposed in the memory semiconductor dies and configured to perform local sub processes corresponding to other portions of the data process and a plurality of memory integrated circuits respectively disposed in the memory semiconductor dies and configured to store data associated with the data process.

Abstract: A memory device includes a memory cell array having a plurality of memory cell groups with a corresponding plurality of independent channels, and the device and an operating method thereof perform an internal data processing operation for the memory cell groups. The memory device includes an internal command generator configured to generate one or more internal commands in order to perform an internal data processing operation in response to a reception of a command, and an internal common bus for a common internal processing channel which is disposed to be shared by the plurality of memory cell groups and configured to form a transmission path of data between the plurality of memory cell groups when the internal data processing operation is performed.

Abstract: A memory device includes a memory cell array having a plurality of memory cell groups with a corresponding plurality of independent channels, and the device and an operating method thereof perform an internal data processing operation for the memory cell groups. The memory device includes an internal command generator configured to generate one or more internal commands in order to perform an internal data processing operation in response to a reception of a command, and an internal common bus for a common internal processing channel which is disposed to be shared by the plurality of memory cell groups and configured to form a transmission path of data between the plurality of memory cell groups when the internal data processing operation is performed.

Abstract: A memory device includes a memory cell array having a plurality of memory cell groups with a corresponding plurality of independent channels, and the device and an operating method thereof perform an internal data processing operation for the memory cell groups. The memory device includes an internal command generator configured to generate one or more internal commands in order to perform an internal data processing operation in response to a reception of a command, and an internal common bus for a common internal processing channel which is disposed to be shared by the plurality of memory cell groups and configured to form a transmission path of data between the plurality of memory cell groups when the internal data processing operation is performed.

Abstract: Disclosed is a computer system which includes a host and a memory module. The host transfers a plurality of cache lines to a memory module through a plurality of channels, the cache lines including a plurality of data elements and allocates cache lines with target data elements in the plurality of data elements to one channel of the plurality of channels. The target data elements are arranged within the ache lines according to a stride interval. The stride interval is a number of data elements between consecutive ones of the target data elements. The memory module includes gather-scatter engines that are respectively connected to the plurality of channels and scatter or gather the target data elements under control of the host.

Abstract: A stacked memory includes a logic semiconductor die, a plurality of memory semiconductor dies stacked with the logic semiconductor die, a plurality of through-silicon vias (TSVs) electrically connecting the logic semiconductor die and the memory semiconductor dies, a global processor disposed in the logic semiconductor die and configured to perform a global sub process corresponding to a portion of a data process, a plurality of local processors respectively disposed in the memory semiconductor dies and configured to perform local sub processes corresponding to other portions of the data process and a plurality of memory integrated circuits respectively disposed in the memory semiconductor dies and configured to store data associated with the data process.

Abstract: A memory device includes a memory cell array having a plurality of memory cell groups with a corresponding plurality of independent channels, and the device and an operating method thereof perform an internal data processing operation for the memory cell groups. The memory device includes an internal command generator configured to generate one or more internal commands in order to perform an internal data processing operation in response to a reception of a command, and an internal common bus for a common internal processing channel which is disposed to be shared by the plurality of memory cell groups and configured to form a transmission path of data between the plurality of memory cell groups when the internal data processing operation is performed.