Abstract: A channel-less design-for-test (DFT) architecture implements distributed test functionality across hardware modules (HMs) of an integrated circuit. The architecture includes a center HM and peripheral HMs interconnected by a standardized bus that carries DFT data communication. Each HM incorporates DFT circuitry comprising a scan shift network (SSN) and an encoder/decoder for test (EDT) circuit to perform local test operations. The center HM includes SSN multiplexing circuitry that manages SSN connections for coordinated test operations across the HMs. This distributed architecture eliminates the need for dedicated test routing channels between modules while enabling independent DFT operations within each HM. The standardized bus interface reduces routing complexity and supports efficient test data communication between modules.

Abstract: This disclosure provides systems, methods, and devices that support enhanced circuit design operations, including floating port identification and floating port-based modifications, and enhanced circuits with floating port-based modifications. In a first aspect, a method for circuit design includes: analyzing library file information for a design block of a plurality of design blocks for a circuit plan to identify floating port information for the library file information. The method also include identifying unused logic of the design block for the circuit plan based on the floating port information, and adjusting the design block for the circuit plan based on the identified unused logic of the design block for the circuit plan. The method further includes outputting a netlist file for the circuit plan based on the adjusted design block. Other aspects and features are also claimed and described.

Abstract: Aspects of the present disclosure provide cells including integrated switches and/or integrated clamps. In some aspects, a cell includes a circuit having an input and an output, and a switch coupled between a supply rail and the circuit, wherein the switch is configured to receive an enable signal, turn on when the enable signal has a first logic value, and turn off when the enable signal has a second logic value. The cell also includes a first clamp coupled to the output of the circuit, wherein the first clamp is configured to clamp the output of the circuit when the enable signal has the second logic value.

Abstract: Various embodiments may include integrated circuits (ICs) and methods for designing an integrated circuit (IC), such as a system-on-chip (SOC). Embodiments include methods for planning and producing ICs without communication channels, also referred to as channel-less ICs. Embodiments may include overlay hard macros that support routing and communication design without dedicated communication channels being needed between functional hard macros, such as cores of a SOC. Various embodiments may include an IC in which one or more interconnect hard macros and wires connecting a first functional hard macro, a second functional hard macro and the one or more interconnect hard macros are located within a third functional hard macro. In some embodiments, no communication channel may be present between the first functional hard macro, the second functional hard macro, and the third functional hard macro.