Patents by Inventor Pavan Mudunuru

Pavan Mudunuru has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Sequence independent non-overlapping digital signal generator with programmable delay
    Patent number: 7612595
    Abstract: A circuit for generating non-overlapping clock signals includes a programmable delayed reference clock signals circuit to produce a plurality of delayed reference clock signals and a plurality of delay clock signal generators, operatively connected to the programmable delayed reference clock signals circuit, to generate non-overlapping clock signals. Each delay clock signal generator includes a latch or flip-flop to control a delay in a rising edge of a clock signal and to output a first signal, another latch or flip-flop to control a delay in a falling edge of a delayed clock signal and to output a first signal, and a logic circuit to generate the clock signal from the first and second signals. The latches or flip-flops independently control a delay in the rising edge of the clock signal in response to one of the plurality of delayed reference clock signals.
    Type: Grant
    Filed: September 17, 2007
    Date of Patent: November 3, 2009
    Assignee: Melexis Tessenderlo NV
    Inventors: Jungwook Yang, Lane Brooks, Pavan Mudunuru
  • SEQUENCE INDEPENDENT NON-OVERLAPPING DIGITAL SIGNAL GENERATOR WITH PROGRAMMABLE DELAY
    Publication number: 20080224743
    Abstract: A circuit for generating non-overlapping clock signals includes a programmable delayed reference clock signals circuit to produce a plurality of delayed reference clock signals and a plurality of delay clock signal generators, operatively connected to the programmable delayed reference clock signals circuit, to generate non-overlapping clock signals. Each delay clock signal generator includes a latch or flip-flop to control a delay in a rising edge of a clock signal and to output a first signal, another latch or flip-flop to control a delay in a falling edge of a delayed clock signal and to output a first signal, and a logic circuit to generate the clock signal from the first and second signals. The latches or flip-flops independently control a delay in the rising edge of the clock signal in response to one of the plurality of delayed reference clock signals.
    Type: Application
    Filed: September 17, 2007
    Publication date: September 18, 2008
    Inventors: Jungwook Yang, Lane Brooks, Pavan Mudunuru