Patents by Inventor Pavan Reddy K. Aella

Pavan Reddy K. Aella has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11636911
    Abstract: Methods, systems, and devices for leakage source detection are described. In some cases, a testing device may scan a first set of access lines of a memory die that have a first length and a second set of access lines of the memory die that have a second length different than the first length. The testing device may determine a first error rate associated with the first set of access lines and a second error rate associated with the second set of access lines. The testing device may categorize a performance of the memory die based on the first and second error rates. In some cases, the testing device may determine a third error rate associated with a type of error based on the first and second error rates and may categorize the performance of the memory die based on the third error rate.
    Type: Grant
    Filed: July 28, 2021
    Date of Patent: April 25, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Amitava Majumdar, Radhakrishna Kotti, Patrick Daniel White, Pavan Reddy K Aella, Rajesh Kamana
  • Publication number: 20230113960
    Abstract: Methods, systems, and devices for techniques for manufacturing a double electrode memory array are described. A memory device may be fabricated using a sequence of fabrication steps that include depositing a first stack of materials including a conductive layer, an interface layer, and a first electrode layer. The first stack of materials may be etched to form a first set of trenches. A second stack of materials may be deposited on top of the first stack of materials. The second stack may include a second electrode layer in contact with the first electrode layer, a storage layer, and a third electrode layer. The second stack of materials may be etched to form a second set of trenches above the first set of trenches, and filled with a sealing layer and a dielectric material. The sealing layer may not extend substantially into the first set of trenches.
    Type: Application
    Filed: October 12, 2021
    Publication date: April 13, 2023
    Inventors: Anna Maria Conti, Andrea Gotti, Pavan Reddy K. Aella
  • Patent number: 11575085
    Abstract: Methods, systems, and devices for techniques for forming memory structures are described. Forming a memory structure may include etching a stack of material including a conductive line, a first electrode and a sacrificial material to divide the stack of material into multiple sections. The process may further include depositing an oxide material in each of the first quantity of channels to form multiple oxide materials. The sacrificial material may be etched to form a second channel between two oxide materials of the multiple oxide materials. Memory material may be deposited over the two oxide materials and the second channel, which may create a void in the second channel between the memory material and the first electrode. The memory material may be heated to fill the void in the second channel.
    Type: Grant
    Filed: February 2, 2021
    Date of Patent: February 7, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Andrea Gotti, Pavan Reddy K. Aella, Dale W. Collins
  • Publication number: 20220020446
    Abstract: Methods, systems, and devices for leakage source detection are described. In some cases, a testing device may scan a first set of access lines of a memory die that have a first length and a second set of access lines of the memory die that have a second length different than the first length. The testing device may determine a first error rate associated with the first set of access lines and a second error rate associated with the second set of access lines. The testing device may categorize a performance of the memory die based on the first and second error rates. In some cases, the testing device may determine a third error rate associated with a type of error based on the first and second error rates and may categorize the performance of the memory die based on the third error rate.
    Type: Application
    Filed: July 28, 2021
    Publication date: January 20, 2022
    Inventors: Amitava Majumdar, Radhakrishna Kotti, Patrick Daniel White, Pavan Reddy K. Aella, Rajesh Kamana
  • Patent number: 11081203
    Abstract: Methods, systems, and devices for leakage source detection are described. In some cases, a testing device may scan a first set of access lines of a memory die that have a first length and a second set of access lines of the memory die that have a second length different than the first length. The testing device may determine a first error rate associated with the first set of access lines and a second error rate associated with the second set of access lines. The testing device may categorize a performance of the memory die based on the first and second error rates. In some cases, the testing device may determine a third error rate associated with a type of error based on the first and second error rates and may categorize the performance of the memory die based on the third error rate.
    Type: Grant
    Filed: November 14, 2019
    Date of Patent: August 3, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Amitava Majumdar, Radhakrishna Kotti, Patrick Daniel White, Pavan Reddy K Aella, Rajesh Kamana
  • Publication number: 20210234097
    Abstract: Methods, systems, and devices for techniques for forming memory structures are described. Forming a memory structure may include etching a stack of material including a conductive line, a first electrode and a sacrificial material to divide the stack of material into multiple sections. The process may further include depositing an oxide material in each of the first quantity of channels to form multiple oxide materials. The sacrificial material may be etched to form a second channel between two oxide materials of the multiple oxide materials. Memory material may be deposited over the two oxide materials and the second channel, which may create a void in the second channel between the memory material and the first electrode. The memory material may be heated to fill the void in the second channel.
    Type: Application
    Filed: February 2, 2021
    Publication date: July 29, 2021
    Inventors: Andrea Gotti, Pavan Reddy K. Aella, Dale W. Collins
  • Publication number: 20210151119
    Abstract: Methods, systems, and devices for leakage source detection are described. In some cases, a testing device may scan a first set of access lines of a memory die that have a first length and a second set of access lines of the memory die that have a second length different than the first length. The testing device may determine a first error rate associated with the first set of access lines and a second error rate associated with the second set of access lines. The testing device may categorize a performance of the memory die based on the first and second error rates. In some cases, the testing device may determine a third error rate associated with a type of error based on the first and second error rates and may categorize the performance of the memory die based on the third error rate.
    Type: Application
    Filed: November 14, 2019
    Publication date: May 20, 2021
    Inventors: Amitava Majumdar, Radhakrishna Kotti, Patrick Daniel White, Pavan Reddy K. Aella, Rajesh Kamana
  • Patent number: 10930849
    Abstract: Methods, systems, and devices for techniques for forming memory structures are described. Forming a memory structure may include etching a stack of material including a conductive line, a first electrode and a sacrificial material to divide the stack of material into multiple sections. The process may further include depositing an oxide material in each of the first quantity of channels to form multiple oxide materials. The sacrificial material may be etched to form a second channel between two oxide materials of the multiple oxide materials. Memory material may be deposited over the two oxide materials and the second channel, which may create a void in the second channel between the memory material and the first electrode. The memory material may be heated to fill the void in the second channel.
    Type: Grant
    Filed: June 28, 2019
    Date of Patent: February 23, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Andrea Gotti, Pavan Reddy K. Aella, Dale W. Collins
  • Publication number: 20200411761
    Abstract: Methods, systems, and devices for techniques for forming memory structures are described. Forming a memory structure may include etching a stack of material including a conductive line, a first electrode and a sacrificial material to divide the stack of material into multiple sections. The process may further include depositing an oxide material in each of the first quantity of channels to form multiple oxide materials. The sacrificial material may be etched to form a second channel between two oxide materials of the multiple oxide materials. Memory material may be deposited over the two oxide materials and the second channel, which may create a void in the second channel between the memory material and the first electrode. The memory material may be heated to fill the void in the second channel.
    Type: Application
    Filed: June 28, 2019
    Publication date: December 31, 2020
    Inventors: Andrea Gotti, Pavan Reddy K. Aella, Dale W. Collins