Patents by Inventor Pavan Y. Bashaboina

Pavan Y. Bashaboina has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8954901
    Abstract: Variation of a parameter of interest is reduced over a field of interest in, for example, an object design, such as a circuit design. The field of interest is divided into tiles. A parameter value is found for each tile and for a group of tiles around each tile. Using these values, variation of the parameter is determined. An adjusted value of the parameter for each tile is determined taking limits into account, iterating until variation is below a threshold value. Parameter uniformity is improved in some applications by over 30% with runtime reduced by an order of magnitude.
    Type: Grant
    Filed: December 2, 2010
    Date of Patent: February 10, 2015
    Assignee: International Business Machines Corporation
    Inventors: Pavan Y. Bashaboina, Brent A. Goplen, Howard S. Landis
  • Patent number: 8458625
    Abstract: Potential lithographic hot spots associated with a lithographic level are marked by a marker layer identifying a marked region. Multiplicate layers are generated for each design shape in that lithographic level in each marked region. Each multiplicate layer includes a different type of variant for each design shape in the lithographic level. The different types of variants correspond to different design environments. Lithographic simulation is performed with each type of variants under the constraint of long range effects, such as pattern density, provided by adjacent shapes in the lithographic level. In each marked region, the results of lithographic simulations are evaluated to determine an optimal type among the variants. The optimal type is retained for the lithographic level in each marked region, thereby providing a chip design layout in which various marked regions can include different types of variant shapes to provide local lithographic optimization.
    Type: Grant
    Filed: July 29, 2011
    Date of Patent: June 4, 2013
    Assignee: International Business Machines Corporation
    Inventors: Pavan Y. Bashaboina, James A. Culp
  • Publication number: 20130031519
    Abstract: Potential lithographic hot spots associated with a lithographic level are marked by a marker layer identifying a marked region. Multiplicate layers are generated for each design shape in that lithographic level in each marked region. Each multiplicate layer includes a different type of variant for each design shape in the lithographic level. The different types of variants correspond to different design environments. Lithographic simulation is performed with each type of variants under the constraint of long range effects, such as pattern density, provided by adjacent shapes in the lithographic level. In each marked region, the results of lithographic simulations are evaluated to determine an optimal type among the variants. The optimal type is retained for the lithographic level in each marked region, thereby providing a chip design layout in which various marked regions can include different types of variant shapes to provide local lithographic optimization.
    Type: Application
    Filed: July 29, 2011
    Publication date: January 31, 2013
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Pavan Y. Bashaboina, James A. Culp
  • Patent number: 8347259
    Abstract: Critical circuit blocks are identified in a chip design layout, and are marked by a marker layer identifying a marked region. Multiplicate layers are generated for each critical circuit block within each marked region. Each multiplicate layer includes a different type of variant for each identified critical circuit block. The different types of variants correspond to different types of optimization goals to address different issues in circuit performance. Circuit simulation is performed with each type of variants in combination with adjacent circuit blocks as provided in original design. In each marked region, the results of the circuit simulations are evaluated to determine an optimal type among the variants. The optimal type is retained in each marked region, thereby providing a chip design layout in which various marked regions can include different types of variant circuit blocks to provide local circuit optimization.
    Type: Grant
    Filed: July 29, 2011
    Date of Patent: January 1, 2013
    Assignee: International Business Machines Corporation
    Inventors: Pavan Y. Bashaboina, James A. Culp
  • Publication number: 20120144354
    Abstract: Variation of a parameter of interest is reduced over a field of interest in, for example, an object design, such as a circuit design. The field of interest is divided into tiles. A parameter value is found for each tile and for a group of tiles around each tile. Using these values, variation of the parameter is determined. An adjusted value of the parameter for each tile is determined taking limits into account, iterating until variation is below a threshold value. Parameter uniformity is improved in some applications by over 30% with runtime reduced by an order of magnitude.
    Type: Application
    Filed: December 2, 2010
    Publication date: June 7, 2012
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Pavan Y. Bashaboina, Brent A. Goplen, Howard S. Landis