Patents by Inventor Pavanish Nirula

Pavanish Nirula has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Automated local clock placement for FPGA designs
    Patent number: 7240315
    Abstract: A method (500) of placing local clock nets in a circuit design can include identifying the local clock nets for the circuit design and selecting components corresponding to each local clock net (510,515), and assigning initial locations to each component of the local clock nets (520). The method further can include generating at least one cost function (530, 550) to evaluate (555) different placements of components of the local clock nets. The components (220, 240) of the local clock nets (205) can be annealed (535–575) using one or more of the cost functions to assign locations to each component of the local clock nets.
    Type: Grant
    Filed: August 29, 2003
    Date of Patent: July 3, 2007
    Assignee: Xilinx, Inc.
    Inventors: Qiang Wang, Sudip K. Nag, Srinivasan Dasasathyan, James L. Saunders, Pavanish Nirula