Patents by Inventor Pavankumar Chandrasekhar

Pavankumar Chandrasekhar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Domino logic testing systems and methods
    Patent number: 7332938
    Abstract: A domino logic test circuit includes a dynamic node, a precharge device for charging the dynamic node, and an output inverter for inverting an output of the dynamic node. A logic network is coupled to the dynamic node for discharging the dynamic node in accordance with logic. A footer device enables and disables the logic network. A keeper device is coupled to the dynamic node for retaining a charge state of the dynamic node while awaiting the logic network to operate in accordance with the logic. A test mode selection device is coupled to the dynamic node and is configured to enable a latch in the test mode. A phase selection device is configured to receive at least a wait signal and to enable selection of at least a precharge phase for charging the dynamic node to a voltage level, a write phase for generating a value to the latch based on the logic and the voltage level of the dynamic node, and a wait phase for enabling reading the value. The selection is based, at least partially, on the wait signal state.
    Type: Grant
    Filed: June 23, 2006
    Date of Patent: February 19, 2008
    Assignee: The Curators of the University of Missouri
    Inventors: Waleed K. Al-Assadi, Pavankumar Chandrasekhar
  • DOMINO LOGIC TESTING SYSTEMS AND METHODS
    Publication number: 20070296465
    Abstract: A domino logic test circuit includes a dynamic node, a precharge device for charging the dynamic node, and an output inverter for inverting an output of the dynamic node. A logic network is coupled to the dynamic node for discharging the dynamic node in accordance with logic. A footer device enables and disables the logic network. A keeper device is coupled to the dynamic node for retaining a charge state of the dynamic node while awaiting the logic network to operate in accordance with the logic. A test mode selection device is coupled to the dynamic node and is configured to enable a latch in the test mode. A phase selection device is configured to receive at least a wait signal and to enable selection of at least a precharge phase for charging the dynamic node to a voltage level, a write phase for generating a value to the latch based on the logic and the voltage level of the dynamic node, and a wait phase for enabling reading the value. The selection is based, at least partially, on the wait signal state.
    Type: Application
    Filed: June 23, 2006
    Publication date: December 27, 2007
    Inventors: Waleed K. Al-Assadi, Pavankumar Chandrasekhar