Abstract: A method for two-pass scheduling of a plurality of tasks generally including steps (A) to (C). Step (A) may assign each of the tasks to a corresponding one or more of a plurality of processors in a first pass through the tasks. The first pass may be non-iterative. Step (B) may reassign the tasks among the processors to shorten a respective load on one or more of the processors in a second pass through the tasks. The second pass may be non-iterative and may begin after the first pass has completed. Step (C) may generate a schedule in response to the assigning and the reassigning. The schedule generally maps the tasks to the processors.

Abstract: A method to generate an erasure locator polynomial in an error-and-erasure decode. The method generally includes the steps of (A) storing current values in multiple registers at a current moment, (B) generating first values by multiplying each current value by a respective one of multiple constants, (C) generating second values by gating at least all but one of the first values with a current one of multiple erasure values of an erasure position vector, (D) generating next values by combining each one of the second values with a corresponding one of the first values, (E) loading the next values into the registers in place of the current values at a next moment and (F) generating an output signal carrying the current values at a last moment such that the current values form the coefficients of the erasure locator polynomial.

Abstract: A circuit having a first circuit and a memory is disclosed. The first circuit may be configured to (i) receive a control signal that identifies a current one of a plurality of wireless communication standards and a code word size and (ii) generate a plurality of tables corresponding to both the current wireless communication standard and the code word size. Each of the tables generally has a plurality of indices. Up to two of the indices may be generated by the first circuit per clock cycle. Each of the tables generally comprises a permutation table of a turbo code interleaver. The memory may be configured to store the tables.

Abstract: An apparatus generally having a first circuit, a second circuit and a third circuit is disclosed. The first circuit may be configured to calculate a plurality of preliminary syndromes from a plurality of received symbols. The second circuit may be configured to calculate a plurality of normal syndromes by modifying the preliminary syndromes using at most two Galois Field multiplications. The third circuit is generally configured to calculate an errata polynomial based on the normal syndromes.

Abstract: An apparatus having a first circuit and a second circuit is disclosed. The first circuit may (i) generate a decoded codeword by decoding a first codeword a plurality of times based on a respective plurality of erasure location vectors and (ii) assert a fail signal upon each failure of the decoding of the first codeword, the decoding comprising an error-and-erasure Reed-Solomon decoding. The second circuit may (i) generate a count of the assertions of the fail signal and (ii) generate the erasure location vectors based on (a) the count and (b) a plurality of reliability items corresponding to the first codeword.

Abstract: A system having an entropy module, a memory module and a main module is disclosed. The entropy module may be configured to generate a plurality of first random numbers. The memory module may be configured to buffer (i) the first random numbers and (ii) a plurality of second random numbers. The main module is generally configured to (i) control a first transfer of the first random numbers from the entropy module to the memory module, (ii) control a second transfer of the first random numbers from the memory module to the main module, (iii) generate the second random numbers by encrypting the first random numbers and (iv) control a third transfer of the second random numbers from the main module to the memory module. The generation of the first random numbers and the generation of the second random numbers may be performed in parallel.

Abstract: A method to generate an erasure locator polynomial in an error-and-erasure decode. The method generally includes the steps of (A) storing current values in multiple registers at a current moment, (B) generating first values by multiplying each current value by a respective one of multiple constants, (C) generating second values by gating at least all but one of the first values with a current one of multiple erasure values of an erasure position vector, (D) generating next values by combining each one of the second values with a corresponding one of the first values, (E) loading the next values into the registers in place of the current values at a next moment and (F) generating an output signal carrying the current values at a last moment such that the current values form the coefficients of the erasure locator polynomial.

Abstract: The present invention is a configurable binary BCH encoder having a variable number of errors. The encoder may implement a universal multipole block which may be configured for receiving an error number input, which may include a maximum error number limit for the encoder, and for calculating a plurality of error coefficients based on the error number input. The encoder may be further configured for receiving a plurality of information bits of an information word. The encoder may be further configured for transmitting/outputting a first (ex.—unmodified) subset of the information bits as an encoder output. The encoder may be further configured for calculating a plurality of parity bits based on a second subset of the information bits and the error coefficients. The encoder may be further configured for transmitting/outputting the calculated parity bits as part of the encoder output.