Abstract: A machine-implemented method of generating trapping-set information for use in LDPC-decoding processing of read signals generated, e.g., by sensing a storage medium, such as a magnetic platter. In one embodiment, the method can be implemented as an add-on to any other trapping-set search method in which the discovered trapping sets are evaluated to determine their influence on the overall bit-error rate and/or error-floor characteristics of the LDPC decoder. The method can advantageously reuse at least some of the computational results obtained during this evaluation, thereby requiring a relatively small amount of additional computations, while providing a significant benefit of discovering many more trapping sets in addition to the ones that are being evaluated.

Abstract: In one embodiment, a machine-implemented method programs a heterogeneous multi-processor computer system to run a plurality of program modules, wherein each program module is to be run on one of the processors The system includes a plurality of processors of two or more different processor types. According to the recited method, machine-implemented offline processing is performed using a plurality of SIET tools of a scheduling information extracting toolkit (SIET) and a plurality of SBT tools of a schedule building toolkit (SBT). A program module applicability analyzer (PMAA) determines whether a first processor of a first processor type is capable of running a first program module without compiling the first program module. Machine-implemented online processing is performed using realtime data to test the scheduling software and the selected schedule solution.

Abstract: A packet-router architecture in which buffer modules are interconnected by one or more interconnect fabrics and arranged to form a plurality of hierarchical buffer levels, with each higher buffer level having more buffer modules than a corresponding lower buffer level. An interconnect fabric is configured to connect three or more respective buffer modules, with one of these buffer modules belonging to one buffer level and the other two or more buffer modules belonging to a next higher buffer level. A buffer module is configured to implement a packet queue that (i) enqueues received packets at the end of the queue in the order of their arrival to the buffer module, (ii) dequeues packets from the head of the queue, and (iii) advances packets toward the head of the queue when the buffer module transmits one or more packets to the higher buffer level or to a respective set of output ports connected to the buffer module.

Abstract: A video transcoder for converting a compressed input video bit-stream having one spatial resolution into a compressed output video bit-stream having a different spatial resolution in a manner that enables the transcoder to dynamically change the amount of computational resources allocated to the conversion process. In one embodiment, the video transcoder has a plurality of configurable processing paths whose configuration determines the amount of allocated computational resources. Exemplary processing-path configuration changes may include, but are not limited to engaging or disengaging a processing path, redirecting a data flow from flowing through one processing path to flowing through another processing path, and attaching or detaching one or more processing modules to an engaged processing path.

Abstract: A machine-based method for modifying a parity-check matrix in a manner that controllably and quantifiably raises the corresponding error-floor level and/or rate of miscorrection to make these quantities observable in direct read-channel simulations that can be completed in a relatively short amount of time. In one embodiment, the method is used to compare different turbo-decoding schemes by comparing the read-channel performance characteristics corresponding to a modified matrix, instead of the original parity-check matrix. In another embodiment, the method is used to validate a heuristic error-rate estimation tool. After being validated, the heuristic error-rate estimation tool can advantageously be used to obtain, in a relatively short amount of time, relatively accurate estimates of the error rates corresponding to the original parity-check matrix.

Abstract: A machine-implemented method of generating trapping-set information for use in LDPC-decoding processing of read signals generated, e.g., by sensing a storage medium, such as a magnetic platter. In one embodiment, the method can be implemented as an add-on to any other trapping-set search method in which the discovered trapping sets are evaluated to determine their influence on the overall bit-error rate and/or error-floor characteristics of the LDPC decoder. The method can advantageously reuse at least some of the computational results obtained during this evaluation, thereby requiring a relatively small amount of additional computations, while providing a significant benefit of discovering many more trapping sets in addition to the ones that are being evaluated.

Abstract: A computer-aided design method for developing, simulating, and testing a read-channel architecture to be implemented in a VLSI circuit. The method uses a coset operating mode and nonzero-syndrome-based decoding to accelerate the simulation of the read-channel's error-rate characteristics corresponding to different parity-check matrices employed in the read-channel's turbo-decoder, such as a low-density parity-check decoder. The acceleration is achieved through recycling some previously generated log-likelihood-ratio values, which enables the method to sometimes bypass certain time-consuming processing steps therein.

Abstract: A computer-aided design method for developing, simulating, and testing a read-channel architecture to be implemented in a VLSI circuit. The method uses codeword/waveform classification to accelerate simulation of the read-channel's error-rate characteristics, with said classification being generated using a first read-channel simulator having a limited functionality. A second read-channel simulator having an extended functionality is then run only for some of the codewords, with the latter having been identified based on said codeword/waveform classification. The acceleration is achieved, at least in part, because the relatively highly time-consuming processing steps implemented in the second read-channel simulator are applied to fewer codewords than otherwise required by conventional simulation methods.

Abstract: A computer-aided design method for developing, simulating, and testing a read-channel architecture to be implemented in a VLSI circuit. The method uses a coset operating mode and nonzero-syndrome-based decoding to accelerate the simulation of the read-channel's error-rate characteristics corresponding to different parity-check matrices employed in the read-channel's turbo-decoder, such as a low-density parity-check decoder. The acceleration is achieved through recycling some previously generated log-likelihood-ratio values, which enables the method to sometimes bypass certain time-consuming processing steps therein.

Abstract: A packet-router architecture in which buffer modules are interconnected by one or more interconnect fabrics and arranged to form a plurality of hierarchical buffer levels, with each higher buffer level having more buffer modules than a corresponding lower buffer level. An interconnect fabric is configured to connect three or more respective buffer modules, with one of these buffer modules belonging to one buffer level and the other two or more buffer modules belonging to a next higher buffer level. A buffer module is configured to implement a packet queue that (i) enqueues received packets at the end of the queue in the order of their arrival to the buffer module, (ii) dequeues packets from the head of the queue, and (iii) advances packets toward the head of the queue when the buffer module transmits one or more packets to the higher buffer level or to a respective set of output ports connected to the buffer module.

Abstract: In one embodiment, a simulator, e.g., for a hard-disk drive selects for testing a signal-to-noise ratio (SNR) value from a range of ratios and an error-correction codeword pattern from a range of codeword patterns. The simulator simulates a communications channel by applying write noise, inter-symbol interference, and read noise to the codeword pattern to generate a noisy signal. In addition, the simulator adds arbitrary-noise to the codeword to accelerate the speed of the simulation. The arbitrary noise increases the probability of converging on a trapping set and does not represent any noise introduced by the communications channel. The simulator attempts to decode the noisy signal, and if decoding is unsuccessful, then the simulator increments an error counter corresponding to the selected signal-to-noise ratio. This process is repeated for all possible combinations of signal-to-noise ratio values and codeword patterns to determine the error rate for all of the signal-to-noise ratio values.

Abstract: In one embodiment, a machine-implemented method programs a heterogeneous multi-processor computer system to run a plurality of program modules, wherein each program module is to be run on one of the processors The system includes a plurality of processors of two or more different processor types. According to the recited method, machine-implemented offline processing is performed using a plurality of SIET tools of a scheduling information extracting toolkit (SIET) and a plurality of SBT tools of a schedule building toolkit (SBT). A program module applicability analyzer (PMAA) determines whether a first processor of a first processor type is capable of running a first program module without compiling the first program module. Machine-implemented online processing is performed using realtime data to test the scheduling software and the selected schedule solution.

Abstract: In one embodiment, a heterogeneous multi-processor computer system includes (i) a plurality of dedicated processors (DPs), each DP configured to implement one or more program modules during runtime operations; (ii) two or more control processors (CPs), each CP configured to run scheduling software for controlling the runtime operations by a corresponding subset of DPs; and (iii) one or more buses interconnecting the DPs and CPs. Each CP is configured to vary timing of implementation of the program modules for the corresponding subset of DPs based on resource availability, and each CP is configured to vary timing of data transfers by the corresponding subset of DPs based on resource availability.

Abstract: In one embodiment, a machine-implemented method programs a heterogeneous multi-processor computer system to run a plurality of program modules, wherein each program module is to be run on one of the processors. The system comprising a plurality of processors of two or more different processor types. Machine-implemented offline processing is performed using a plurality of SIET tools of a scheduling information extracting toolkit (SIET) and a plurality of SBT tools of a schedule building toolkit (SBT). Machine-implemented online processing is performed using realtime data to test the scheduling software and the selected schedule solution. A Source Code Generator (SCG) integrates scheduling information for the selected schedule solution into the scheduling software for a first processor such that the scheduling information is compiled with the scheduling software.

Abstract: A search method for identifying an intra mode that can produce acceptable video-encoding quality for a pixel block while striking a proper balance between the quality and processor load. In a representative embodiment, the search method relies on a set of mode-selection rules for iteratively identifying candidate intra modes. Each identified candidate is evaluated based on a comparison of its sum of absolute differences (SAD) with the smallest SAD in the set of the previously identified candidates. The mode-selection rules use the comparison results as conditions that efficiently guide the search method toward an intra mode that is suitable for encoding the pixel block with acceptable video quality. On average, a representative embodiment of the search method disclosed herein is advantageously capable of finding a suitable intra mode in fewer iterations than a comparable prior-art search method.

Abstract: In one embodiment, a pause-based music detection (MD) module detects music by analyzing pauses in a received audio signal. The energy of each frame of the signal is compared to an energy threshold to determine whether the frame corresponds to background noise only (i.e., a pause) or sound such as speech or music. A window having a number of frames is analyzed to determine whether there is a pause within the window. If no pauses are detected in the window, then the current frame is presumed to correspond to music. If a pause is detected, then the current frame is presumed to correspond to speech. In another embodiment, the pause-based MD module output is applied to Boolean “OR” logic along with a tone-based MD module output to generate a final MD decision. The tone-based MD module detects music by analyzing tones in the signal using any suitable tone-based MD algorithm.

Abstract: A video transcoder for converting a compressed input video bit-stream having one spatial resolution into a compressed output video bit-stream having a different spatial resolution using a plurality of resizing channels. The transcoder has a kernel that partially decodes the compressed input video bit-stream to generate partially decoded video data. The data segments corresponding to picture portions that have both intra- and inter-predicted blocks in close spatial proximity to one another are applied to a mixed-mode resizing channel that is specifically designed for processing such data segments. For each received data segment, the control logic of the channel selects, from a bank of pre-configured resizers, a resizer that is deemed to be most suitable for resizing the image portion represented by that data segment in a computationally efficient manner. The data segment is processed in the selected resizer to generate the corresponding resized-image data.

Abstract: A video transcoder for converting a compressed input video bit-stream having one spatial resolution into a compressed output video bit-stream having a different spatial resolution in a manner that enables the transcoder to dynamically change the amount of computational resources allocated to the conversion process. In one embodiment, the video transcoder has a plurality of configurable processing paths whose configuration determines the amount of allocated computational resources. Exemplary processing-path configuration changes may include, but are not limited to engaging or disengaging a processing path, redirecting a data flow from flowing through one processing path to flowing through another processing path, and attaching or detaching one or more processing modules to an engaged processing path.