Abstract: Programming a fuse for a one-time programmable (OTP) memory can require applying a programming current for a programming period to increase a resistance of the fuse. It may be desirable for the resistance to be very high. A very high resistance may be achieved by applying a high programming current to form a void in the fuse. Applying the high programming current too long after the void is formed, however, may lead to uncontrolled variations and ultimately damage. Accordingly, it may be desirable to end the programming period sometime after the void is formed but before the uncontrolled variations begin. Ideally the programming period is ended at a time at which the programming current is minimum. The disclosed circuits and method provide a means to estimate this time without requiring the complexity of sensing very low levels of programming current.

Abstract: A method and semiconductor device for controlling skip mode operation during light load conditions in a resonant power converter includes a skip mode controller circuit that compares a feedback signal corresponding to the secondary output level with a reference voltage to determine when to invoke skip mode. When entering skip mode the skip mode controller ceases switching by turning on the lower switch for a prolonged time to leave the resonant capacitor partially charged. Upon resuming switching, the lower switch is turned on first to drive current through the inductances, and asymmetric switching is used where the upper switch is on, initially for shorter periods to allow zero voltage switching. If the load increases, the on-time of upper and lower switches converge and conventional symmetric switching resumes.

Abstract: A method and semiconductor device for a resonant power converter includes logic circuitry that performs a dedicated startup sequence when power is first provided to the resonant converter. The logic circuitry can discharge the resonant capacitor, then iteratively pulse only an upper switch during a portion of the startup sequence, and measures the dead time between the half bridge signal starting to fall and the next time it finishes rising. If the dead time is greater that a startup exit value, which is based on the most recent upper switch on-time, then the upper switch on-time is incremented and the process is repeated until the dead time is less than the startup exit value, whereupon the startup logic transitions to conventional symmetric switching.

Abstract: A method and semiconductor device for controlling skip mode operation during light load conditions in a resonant power converter includes a skip mode controller circuit that compares a feedback signal corresponding to the secondary output level with a reference voltage to determine when to invoke skip mode. When entering skip mode the skip mode controller ceases switching by turning on the lower switch for a prolonged time to leave the resonant capacitor partially charged. Upon resuming switching, the lower switch is turned on first to drive current through the inductances, and asymmetric switching is used where the upper switch is on, initially for shorter periods to allow zero voltage switching. If the load increases, the on-time of upper and lower switches converge and conventional symmetric switching resumes.

Abstract: A method and semiconductor device for a resonant power converter includes logic circuitry that performs a dedicated startup sequence when power is first provided to the resonant converter. The logic circuitry can discharge the resonant capacitor, then iteratively pulse only an upper switch during a portion of the startup sequence, and measures the dead time between the half bridge signal starting to fall and the next time it finishes rising. If the dead time is greater that a startup exit value, which is based on the most recent upper switch on-time, then the upper switch on-time is incremented and the process is repeated until the dead time is less than the startup exit value, whereupon the startup logic transitions to conventional symmetric switching.

Abstract: In accordance with an embodiment, a controller includes a comparator, a delay element, and a timer. The delay element is connected to an input terminal of the comparator and the timer is connected to an output terminal of the comparator. The delay element may include a switch having a control electrode coupled for receiving a control signal. In accordance with another embodiment, a detection signal is generated in response to a comparison signal transitioning to a first level.

Abstract: In accordance with an embodiment, a controller includes a comparator, a delay element, and a timer. The delay element is connected to an input terminal of the comparator and the timer is connected to an output terminal of the comparator. The delay element may include a switch having a control electrode coupled for receiving a control signal. In accordance with another embodiment, a detection signal is generated in response to a comparison signal transitioning to a first level.

Abstract: In one embodiment, a PWM controller is configured to form a drive signal that has an operating frequency that varies around a center by a percentage of the center frequency.

Abstract: In one embodiment, a PWM controller is configured to form a drive signal that has an operating frequency that varies around a center by a percentage of the center frequency.

Abstract: In one embodiment, a PWM controller is configured to form a control signal that has reduced noise. The control signal is used to adjust a frequency of a clock signal of the PWM controller.