Patents by Inventor Pavel Panus

Pavel Panus has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8897467
    Abstract: An electronic amplifier for driving a capacitive load may include first and second differential input terminals to receive an input signal, and first and second differential output terminals to provide a differential output signal. The amplifier may further include a first operational device having first and second differential inputs connected to the first and second differential input terminals, respectively, and an output connected to the first differential output terminal, and a second operational device having first and second differential inputs connected to the first and second differential input terminals, respectively, and an output connected to the second differential output terminal. The first and second operational devices may be operatively configured so that both the first and the second output terminals are at a same reference potential during periods in which a magnitude of differential output signal amplitude decreases.
    Type: Grant
    Filed: December 22, 2010
    Date of Patent: November 25, 2014
    Assignee: STMicroelectronics Design and Application S.R.O.
    Inventors: Peter Murin, Tomas Folk, Pavel Panus
  • Patent number: 8058926
    Abstract: A switch including a first transistor including a first main terminal connected to a first switch node, a second main terminal connected to a second switch node and a control terminal, the second switch node being connected to a first clean voltage supply, and first control circuitry connected to the control terminal of the first transistor, including a first node connected to the first clean voltage supply, a second node connected to a second voltage level, and a control input node for receiving a first input control signal variable between a supply voltage level and a third voltage level, the first control means arranged to selectively connect the control terminal of the first transistor to one of the first node and the second node based on the first input control signal.
    Type: Grant
    Filed: January 19, 2007
    Date of Patent: November 15, 2011
    Assignees: STMicroelectronics Design and Application s.r.o., STMicroelectronics S.A.
    Inventors: Hynek Saman, Peter Murin, Martin Boksa, Pavel Panus
  • Publication number: 20110150245
    Abstract: An electronic amplifier for driving a capacitive load may include first and second differential input terminals to receive an input signal, and first and second differential output terminals to provide a differential output signal. The amplifier may further include a first operational device having first and second differential inputs connected to the first and second differential input terminals, respectively, and an output connected to the first differential output terminal, and a second operational device having first and second differential inputs connected to the first and second differential input terminals, respectively, and an output connected to the second differential output terminal. The first and second operational devices may be operatively configured so that both the first and the second output terminals are at a same reference potential during periods in which a module of differential output signal amplitude decrease.
    Type: Application
    Filed: December 22, 2010
    Publication date: June 23, 2011
    Applicant: STMicroelectronics Design and Application S.R.O.
    Inventors: Peter MURIN, Tomas Folk, Pavel Panus
  • Patent number: 7538604
    Abstract: A circuit including a first sensitive node, a first component connected between the first sensitive node and a first terminal of a first switch, said first switch controlled by a first control signal variable between a supply voltage level and a second voltage level, and a second switch including a first terminal connected to the first terminal of said first switch, and a second terminal connected to a clean voltage supply, said second switch controlled to connect the first node of said first switch to said clean voltage supply when said first switch is in a non-conducting state.
    Type: Grant
    Filed: January 19, 2007
    Date of Patent: May 26, 2009
    Assignees: STMicroelectronics S.A., STMicroelectronics Design and Application s.r.o.
    Inventors: Hynek Saman, Peter Murin, Martin Boksa, Pavel Panus
  • Publication number: 20070170974
    Abstract: A circuit including a first sensitive node, a first component connected between the first sensitive node and a first terminal of a first switch, said first switch controlled by a first control signal variable between a supply voltage level and a second voltage level, and a second switch including a first terminal connected to the first terminal of said first switch, and a second terminal connected to a clean voltage supply, said second switch controlled to connect the first node of said first switch to said clean voltage supply when said first switch is in a non-conducting state.
    Type: Application
    Filed: January 19, 2007
    Publication date: July 26, 2007
    Applicants: STMicroelectronics S.A., STMicroelectronics Design and Application s.r.o.
    Inventors: Hynek Saman, Peter Murin, Martin Boksa, Pavel Panus
  • Publication number: 20070170976
    Abstract: A switch including a first transistor including a first main terminal connected to a first switch node, a second main terminal connected to a second switch node and a control terminal, the second switch node being connected to a first clean voltage supply, and first control circuitry connected to the control terminal of the first transistor, including a first node connected to the first clean voltage supply, a second node connected to a second voltage level, and a control input node for receiving a first input control signal variable between a supply voltage level and a third voltage level, the first control means arranged to selectively connect the control terminal of the first transistor to one of the first node and the second node based on the first input control signal.
    Type: Application
    Filed: January 19, 2007
    Publication date: July 26, 2007
    Applicants: STMicroelectronics S.A., STMicroelectronics Design and Application s.r.o.
    Inventors: Hynek Saman, Peter Murin, Martin Boksa, Pavel Panus