Abstract: First data is transmitted from a modem of a device to a processor of the device over a point-to-point serial data link at a first one of a plurality of link speeds, where the first data is received at the device over a wireless network connection. The data link transitions to an inactive state following transmission of the first data. Second data is identified that has likewise been received over a wireless network connection, where at least a portion of the second data is received at the device while the data link is in the inactive state. A change from the first speed to a second one of the plurality of link speeds is determined based on historical parameters and predictive parameters. The data link is transitioned to an active state operational at the second link speed to transmit the second data to the processor over the data link.

Abstract: In one embodiment, an apparatus includes: a transmitter to send first data to a device coupled to the apparatus via a physical link; a receiver to receive second data from the device via the physical link; and a control circuit to control the transmitter to send the first data at a first effective rate during a link activation interval of a data transfer interval and to control the receiver to receive the second data at a second effective rate during the link activation interval, the second effective rate different than the first effective rate. Other embodiments are described and claimed.

Abstract: A modem identifies an idle condition associated with a data network to be accessed and determines an opportunity to enter a first one of a set of low power device states based on the idle condition, where the set of low power device states further includes a second low power device state, and a host device consumes less power in the first low power device state than in the second low power device state. A notification is sent to an application processor of the host device that the modem is to enter a sleep state, where the notification identifies the first low power device state, and a low power link state is entered corresponding to the first low power device state based on a signal from the application processor. The low power link state applies to a link coupling a communications processor of the modem to the application processor.

Abstract: Systems, methods, and computer-readable media for transferring data between a host platform and modem circuitry are provided. At low data rates, data may be stored by on-chip memory, and data may be transferred from the on-chip memory to the host platform over an interconnect (IX) when a first aggregation period expires. At medium data rates, data may be stored in both the on-chip memory and in in-package or off-chip memory, and the data may be transferred from the on-chip memory and off-chip memory to the host platform over the IX when a second aggregation period expires. At high data rates, the on-chip memory may serve as an elastic buffer, and the data may be streamed directly through the on-chip memory to the host platform over the IX. Other embodiments are described and/or claimed.

Abstract: First data is transmitted from a modem of a device to a processor of the device over a point-to-point serial data link at a first one of a plurality of link speeds, where the first data is received at the device over a wireless network connection. The data link transitions to an inactive state following transmission of the first data. Second data is identified that has likewise been received over a wireless network connection, where at least a portion of the second data is received at the device while the data link is in the inactive state. A change from the first speed to a second one of the plurality of link speeds is determined based on historical parameters and predictive parameters. The data link is transitioned to an active state operational at the second link speed to transmit the second data to the processor over the data link.

Abstract: In one embodiment, an apparatus includes: a transmitter to send first data to a device coupled to the apparatus via a physical link; a receiver to receive second data from the device via the physical link; and a control circuit to control the transmitter to send the first data at a first effective rate during a link activation interval of a data transfer interval and to control the receiver to receive the second data at a second effective rate during the link activation interval, the second effective rate different than the first effective rate. Other embodiments are described and claimed.

Abstract: A modem identifies an idle condition associated with a data network to be accessed and determines an opportunity to enter a first one of a set of low power device states based on the idle condition, where the set of low power device states further includes a second low power device state, and a host device consumes less power in the first low power device state than in the second low power device state. A notification is sent to an application processor of the host device that the modem is to enter a sleep state, where the notification identifies the first low power device state, and a low power link state is entered corresponding to the first low power device state based on a signal from the application processor. The low power link state applies to a link coupling a communications processor of the modem to the application processor.

Abstract: Systems, methods, and computer-readable media for transferring data between a host platform and modem circuitry are provided. At low data rates, data may be stored by on-chip memory, and data may be transferred from the on-chip memory to the host platform over an interconnect (IX) when a first aggregation period expires. At medium data rates, data may be stored in both the on-chip memory and in in-package or off-chip memory, and the data may be transferred from the on-chip memory and off-chip memory to the host platform over the IX when a second aggregation period expires. At high data rates, the on-chip memory may serve as an elastic buffer, and the data may be streamed directly through the on-chip memory to the host platform over the IX. Other embodiments are described and/or claimed.

Abstract: A modem identifies an idle condition associated with a data network to be accessed and determines an opportunity to enter a first one of a set of low power device states based on the idle condition, where the set of low power device states further includes a second low power device state, and a host device consumes less power in the first low power device state than in the second low power device state. A notification is sent to an application processor of the host device that the modem is to enter a sleep state, where the notification identifies the first low power device state, and a low power link state is entered corresponding to the first low power device state based on a signal from the application processor. The low power link state applies to a link coupling a communications processor of the modem to the application processor.

Abstract: A modem identifies an idle condition associated with a data network to be accessed and determines an opportunity to enter a first one of a set of low power device states based on the idle condition, where the set of low power device states further includes a second low power device state, and a host device consumes less power in the first low power device state than in the second low power device state. A notification is sent to an application processor of the host device that the modem is to enter a sleep state, where the notification identifies the first low power device state, and a low power link state is entered corresponding to the first low power device state based on a signal from the application processor. The low power link state applies to a link coupling a communications processor of the modem to the application processor.

Abstract: In a telecommunications or data processing system having at least one active control unit and at least one redundant passive control unit that are respectively provided with at least one memory unit, the following operations are performed: (a) a mirroring routine is invoked when a virtual memory region in a memory unit of an active control unit, having a memory content that is to be mirrored to a memory unit of the at least one redundant passive control unit, is accessed by writing; (b) during execution of the mirroring routine, the memory content to be written is copied into a memory region in the memory unit of the at least one redundant passive control unit; and (c) the writing access to the active control unit, which has led to the invocation of the mirroring routine, is repeated in the mirroring routine, on another virtual memory region that is imaged onto the same address as the memory region.

Abstract: Identically structured processor boards operating in lockstep mode are frequently used for redundant systems. The deterministic behavior of all components comprised in the board, i.e. CPUS, chip sets, main memory, etc. is the basic condition for implementing a lockstep system, deterministic behavior meaning that said components simultaneously supply identical results if the components receive identical stimuli at the same time and if no error occurs. Deterministic behavior also requires the use of clocked interfaces. In many cases, asynchronous interfaces cause a certain temporal fuzziness in the system, preventing the overall behavior of the system from remaining synchronous. In order to nevertheless operate in lockstep mode, the invention relates to a method for synchronizing external events which are fed to and influence a component.

Abstract: With this circuit arrangement and the method associated therewith, time-critical procedures to be processed are adopted on assemblies with direct memory access and non time-critical procedures by processors which are arranged on neighboring assemblies.

Abstract: In a fault-tolerant system which is constructed from two identical control devices, there is a requirement to establish consistent memory contents in both devices in order to guarantee uninterrupted operation in the event of a hardware defect in one of the two control devices. To this end, the memory contents are transferred from an active control device to an inactive control device. In this situation, the active control device remains in operation and the contents of the memory of the active control device can be continually updated. According to the invention, the transfer of the memory contents is performed by a copying device, whereby the copying device manages the memory areas of the memory of the active control device which are to be transferred and which are possibly changing by means of a memory monitoring module and a marking memory.

Abstract: Redundant systems are often provided with identically mounted processor boards which function according to a lockstep operation. The basic condition for the implementation of a lockstep system is the deterministic behaviour of all of the constituents contained in the board, such as CPUs, chip sets, main memory etc. According to the invention, deterministic behaviour signifies that said constituents supply identical results at identical times, in an error-free case, when the constituents receive identical stimuli at identical times. Deterministic behaviour also presupposes the use of interfaces in clock-controlled synchronism. Asynchronous interfaces cause a certain temporal indeterminacy in the system in many cases, whereby the entire synchronised behaviour of the system cannot be maintained. In order to thus be able to carry out a lockstep operation, the invention relates to a method for the synchronisation of external events which are supplied to a processor (CPU) and influence the same.

Abstract: A method implemented in hardware for synchronization of identical or different redundant processing units which process identical instruction sequences and are synchronously or asynchronously clocked. In the method, transactions that are external to the processing unit are used by modules assigned to the processing unit for synchronization of the processing unit in that the processing unit is delayed, in each case, by the assigned modules until the instruction execution of the processing units has reached the current transaction.

Abstract: A detection and correction method for detecting and correcting line defects, as well as a circuit arrangement, are provided to execute a checking routine on every single line, whereby all errors are reliably detected. By virtue of the detection, only one additional fallback line need be provided for each single line error to be corrected, to which fallback line a switchover is made in the event of an error.

Abstract: The invention relates to a bus for a highly scalable multiprocessor system, to a redundant bus system that utilizes this bus, and to a method for transmitting information in this bus system. To guarantee an optimally high throughput of individual accesses onto a shared memory, the bus 3 consists of an address bus 4 and a data bus 5, which are operated logically independent of one another and which are functionally connected only via a common identifier. In this way, the dynamic holding of the address bus 4 and of the data bus 5 as well as the latencies are minimized.

Abstract: An electronic apparatus having a first assembly and a second assembly, which is identical to the first assembly; a bidirectional line, which connects the first and second assemblies to one another and is coupled to a voltage source; a first and a second test data providing device respectively assigned to an assembly; a first and a second line level fixing device, which are respectively assigned to an assembly, connected to the line via an interface and designed in such a way that, in response to a signal generated by the test data providing device, the line is connected to ground or isolated therefrom; a first and a second line level detecting device, which are respectively assigned to an assembly and connected to the line via the interface; and a first and a second evaluation device, which are respectively assigned to an assembly and designed in such a way that lack of correspondence between the signals of the first and second test data providing devices is detected.

Abstract: In a fault-tolerant system which is constructed from two identical control devices, there is a requirement to establish consistent memory contents in both devices in order to guarantee uninterrupted operation in the event of a hardware defect in one of the two control devices. To this end, the memory contents are transferred from an active control device to an inactive control device. In this situation, the active control device remains in operation and the contents of the memory of the active control device can be continually updated. According to the invention, the transfer of the memory contents is performed by a copying device, whereby the copying device manages the memory areas of the memory of the active control device which are to be transferred and which are possibly changing by means of a memory monitoring module and a marking memory.