Patents by Inventor Pavel POLIAKOV

Pavel POLIAKOV has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10930365
    Abstract: In embodiments, a memory controller (MC) includes an output interface, and an execution engine (EE) to identify, based on field test results of a die coupled to the MC, initial test results of the die using an artificial neural network (ANN) trained to identify the die from a set of NVM dies based on initial test results of the set of NVM dies obtained at a time of manufacture of the set of dies. The initial test results include a first useful life prediction and the field test results include a second useful life prediction, and the initial test results are regenerated by the ANN to protect their confidentiality. In embodiments, the MC is further to compare the second useful life prediction with the first useful life prediction, to determine a deviation between the two, and output, via the output interface, the deviation to a user.
    Type: Grant
    Filed: February 21, 2019
    Date of Patent: February 23, 2021
    Assignee: Intel Corporation
    Inventors: Pavel Poliakov, Andrey Kudryavtsev, Shekoufeh Qawami, Amirali Khatib Zadeh, Monte Klinkenborg
  • Patent number: 10847245
    Abstract: A memory controller includes a memory to store results of a reference performance test (RT) performed on a non-volatile memory (NVM) die, where the results of the RT include one or more first indicators of failure associated with one or more first read/write cycles of the NVM die before the NVM die is placed in use. The memory controller further includes an analyzer coupled with the memory to perform, in one or more second read/write cycles, one or more field tests that provide second indicators of failure associated with one or more second read/write cycles of the NVM die during the use of the NVM die, and further to predict and dynamically adjust, over one or more second read/write cycles, at least one of likelihood or expected time of failure of the NVM, based at least in part on the first and second indicators of failure.
    Type: Grant
    Filed: August 24, 2018
    Date of Patent: November 24, 2020
    Assignee: Intel Corporation
    Inventors: Pavel Poliakov, Andrey Kudryavtsev, Shekoufeh Qawami, Amirali Khatib Zadeh
  • Publication number: 20190189236
    Abstract: In embodiments, a memory controller (MC) includes an output interface, and an execution engine (EE) to identify, based on field test results of a die coupled to the MC, initial test results of the die using an artificial neural network (ANN) trained to identify the die from a set of NVM dies based on initial test results of the set of NVM dies obtained at a time of manufacture of the set of dies. The initial test results include a first useful life prediction and the field test results include a second useful life prediction, and the initial test results are regenerated by the ANN to protect their confidentiality. In embodiments, the MC is further to compare the second useful life prediction with the first useful life prediction, to determine a deviation between the two, and output, via the output interface, the deviation to a user.
    Type: Application
    Filed: February 21, 2019
    Publication date: June 20, 2019
    Inventors: Pavel Poliakov, Andrey Kudryavtsev, Shekoufeh Qawami, Amirali Khatib Zadeh, Monte Klinkenborg
  • Publication number: 20190042480
    Abstract: Examples include techniques for determining validity of a memory used with a memory controller. Examples include a system having a memory device including a non-volatile memory and a memory controller, where the memory controller includes a validation component including a hash function and a hash table. In embodiments, the validation component performs, during a time of manufacturing of the memory controller, a test of the non-volatile memory to produce first test results, generates a first hash of the first test results using the hash function, and stores the first hash in the hash table. Later, the validation component performs, during a time of use of the memory controller after the time of manufacturing, the test of the non-volatile memory to produce second test results, generates a second hash of the second test results using the hash function, compares the first hash from the hash table with the second hash, and indicates an invalid memory when the first hash does not match the second hash.
    Type: Application
    Filed: February 5, 2018
    Publication date: February 7, 2019
    Inventors: Amirali KHATIB ZADEH, Pavel POLIAKOV, Shekoufeh QAWAMI
  • Publication number: 20190043602
    Abstract: A memory controller includes a memory to store results of a reference performance test (RT) performed on a non-volatile memory (NVM) die, where the results of the RT include one or more first indicators of failure associated with one or more first read/write cycles of the NVM die before the NVM die is placed in use. The memory controller further includes an analyzer coupled with the memory to perform, in one or more second read/write cycles, one or more field tests that provide second indicators of failure associated with one or more second read/write cycles of the NVM die during the use of the NVM die, and further to predict and dynamically adjust, over one or more second read/write cycles, at least one of likelihood or expected time of failure of the NVM, based at least in part on the first and second indicators of failure.
    Type: Application
    Filed: August 24, 2018
    Publication date: February 7, 2019
    Inventors: Pavel Poliakov, Andrey Kudryavtsev, Shekoufeh Qawami, Amirali Khatib Zadeh