Abstract: A phase locked loop (PLL) provides output signals at multiple frequencies. In particular, the PLL includes a phase detector and two voltage controlled oscillators (VCOs). One of the VCOs is selectively enabled depending on a desired output signal. The phase detector receives a reference signal and a feedback signal from the enabled one of the two VCOs. The phase detector outputs a control signal that controls the VCO that provided the feedback signal.

Abstract: A phase locked loop (PLL) provides output signals at multiple frequencies. In particular, the PLL includes a phase detector and two voltage controlled oscillators (VCOs). One of the VCOs is selectively enabled depending on a desired output signal. The phase detector receives a reference signal and a feedback signal from the enabled one of the two VCOs. The phase detector outputs a control signal that controls the VCO that provided the feedback signal.

Abstract: Frequency synchronizing a local oscillator in a remote unit in a distributed antenna system (DAS) used for frequency shifting communications signals based on a received digital pulse signal from a central unit. A remote unit receives a frequency shifted downlink communications signal and a reference pulse signal indicative of a frequency of a reference oscillator from a central unit. To recover the original signal, a mixing frequency signal generated by a local oscillator is used. To recover a signal having the same frequency as the original signal, the local oscillator should be the same or substantially the same frequency as the frequency used to create the frequency shifted version. A time difference signal indicating the frequency difference between the oscillators is calculated. A frequency adjustment signal is provided to the local oscillator based on the time difference signal to decrease the frequency difference between the oscillators.

Abstract: Frequency synchronizing a local oscillator in a remote unit in a distributed antenna system (DAS) used for frequency shifting communications signals based on a received digital pulse signal from a central unit. A remote unit receives a frequency shifted downlink communications signal and a reference pulse signal indicative of a frequency of a reference oscillator from a central unit. To recover the original signal, a mixing frequency signal generated by a local oscillator is used. To recover a signal having the same frequency as the original signal, the local oscillator should be the same or substantially the same frequency as the frequency used to create the frequency shifted version. A time difference signal indicating the frequency difference between the oscillators is calculated. A frequency adjustment signal is provided to the local oscillator based on the time difference signal to decrease the frequency difference between the oscillators.

Abstract: Embodiments disclosed include variable amplitude signal generators for generating a sinusoidal signal having limited direct current (DC) offset variation and related devices and methods. Instead of employing a single pulse width modulation (PWM) signal to generate a sinusoidal signal, in one embodiment, a circuit is provided that generates two PWM signals. The first PWM signal is a high-to-low PWM signal, where the active state is a lower signal level. The second PWM signal is a low-to-high PWM signal where active state is a higher signal level. The first and second PWM signals are combined to provide a summed signal, which is filtered to generate a sinusoidal signal. The DC offset of the first PWM signal varies inversely to the DC offset of the second PWM signal. In this manner, distortions caused by variations in the DC offset present in the generated sinusoidal signal are limited (i.e., reduced or eliminated).

Abstract: Embodiments disclosed include variable amplitude signal generators for generating a sinusoidal signal having limited direct current (DC) offset variation and related devices and methods. Instead of employing a single pulse width modulation (PWM) signal to generate a sinusoidal signal, in one embodiment, a circuit is provided that generates two PWM signals. The first PWM signal is a high-to-low PWM signal, where the active state is a lower signal level. The second PWM signal is a low-to-high PWM signal where active state is a higher signal level. The first and second PWM signals are combined to provide a summed signal, which is filtered to generate a sinusoidal signal. The DC offset of the first PWM signal varies inversely to the DC offset of the second PWM signal. In this manner, distortions caused by variations in the DC offset present in the generated sinusoidal signal are limited (i.e., reduced or eliminated).