Patents by Inventor Pavel Shamis
Pavel Shamis has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 12001722Abstract: There is provided an apparatus, method, and computer-readable medium. The apparatus comprises interconnect circuitry to couple a device to one or more processing elements and to one or more storage structures. The apparatus also comprises stashing circuitry configured to receive stashing transactions from the device, each stashing transaction comprising payload data and control data. The stashing circuitry is responsive to a given stashing transaction whose control data identifies a plurality of portions of the payload data, to perform a plurality of independent stashing decision operations, each of the plurality of independent stashing decision operations corresponding to a respective portion of the plurality of portions of payload data and comprising determining, with reference to the control data, whether to direct the respective portion to one of the one or more storage structures or whether to forward the respective portion to memory.Type: GrantFiled: August 18, 2022Date of Patent: June 4, 2024Assignee: Arm LimitedInventors: Pavel Shamis, Honnappa Nagarahalli, Jamshed Jalal
-
Publication number: 20240160452Abstract: The present disclosure relates generally to systems, devices and/or processes for runtime linking of software component function implementations, and relates more particularly to linking particular function implementations based at least in part on a current execution environment.Type: ApplicationFiled: December 13, 2022Publication date: May 16, 2024Inventors: Eric Van Hensbergen, Vasileios Laganakos, Pavel Shamis, Luis Emilio Pena
-
Publication number: 20240061613Abstract: There is provided an apparatus, method, and computer-readable medium. The apparatus comprises interconnect circuitry to couple a device to one or more processing elements and to one or more storage structures. The apparatus also comprises stashing circuitry configured to receive stashing transactions from the device, each stashing transaction comprising payload data and control data. The stashing circuitry is responsive to a given stashing transaction whose control data identifies a plurality of portions of the payload data, to perform a plurality of independent stashing decision operations, each of the plurality of independent stashing decision operations corresponding to a respective portion of the plurality of portions of payload data and comprising determining, with reference to the control data, whether to direct the respective portion to one of the one or more storage structures or whether to forward the respective portion to memory.Type: ApplicationFiled: August 18, 2022Publication date: February 22, 2024Inventors: Pavel SHAMIS, Honnappa NAGARAHALLI, Jamshed JALAL
-
Patent number: 11409530Abstract: A system, apparatus and method for ordering a sequence of processing transactions. The method includes accessing, from a memory, a program sequence of operations that are to be executed. Instructions are received, some of them having an identifier, or mnemonic, that is used to distinguish those identified operations from other operations that do not have an identifier, or mnemonic. The mnemonic indicates a distribution of the execution of the program sequence of operations. The program sequence of operations is grouped based on the mnemonic such that certain operations are separated from other operations.Type: GrantFiled: August 16, 2018Date of Patent: August 9, 2022Assignee: Arm LimitedInventors: Curtis Glenn Dunham, Pavel Shamis, Jamshed Jalal, Michael Filippo
-
Patent number: 11237960Abstract: A data processing system includes a processor, a memory system, a cache controller and a cache accessible by the processor via the cache controller. The cache controller provides an asynchronous interface between the processor and the memory system. Instructions, issued by the processor to the cache controller, are completed by the cache controller without blocking the processor. In addition, the cache controller tracks a completion status of the memory operation associated with each instruction and enables the completion status to be queried by the processor. Status of the memory operation may be recorded as an entry in a log, where the log, or a property of the log, is accessible by the processor.Type: GrantFiled: May 21, 2019Date of Patent: February 1, 2022Assignee: Arm LimitedInventors: Curtis Glenn Dunham, Pavel Shamis
-
Patent number: 11176042Abstract: A method and apparatus for monitoring cache transactions in a cache of a data processing system is provided. Responsive to a cache transaction associated with a transaction address, when a cache controller determines that the cache transaction is selected for monitoring, the cache controller retrieves a pointer stored in a register, determines a location in a log memory from the pointer, and writes a transaction identifier to the determined location in the log memory. The transaction identifier is associated with the transaction address and may be a virtual address, for example. The pointer is updated and stored to the register. The architect of the apparatus may include a mechanism for atomically combining data access instructions with an instruction to commence monitoring.Type: GrantFiled: May 21, 2019Date of Patent: November 16, 2021Assignee: Arm LimitedInventors: Curtis Glenn Dunham, Jonathan Curtis Beard, Pavel Shamis, Eric Ola Harald Liljedahl
-
Patent number: 11082493Abstract: Briefly, example methods, apparatuses, and/or articles of manufacture are disclosed that may be implemented, in whole or in part, using one or more mobile communication devices and/or processing devices to facilitate and/or support one or more operations and/or techniques for executing distributed memory operations. In particular, some embodiments are directed to techniques for the traversal of vertices of a data structure maintained in a distributed memory system.Type: GrantFiled: November 16, 2018Date of Patent: August 3, 2021Assignee: Arm LimitedInventors: Pavel Shamis, Alejandro Rico Carro
-
Publication number: 20200371929Abstract: A method and apparatus for monitoring cache transactions in a cache of a data processing system is provided. Responsive to a cache transaction associated with a transaction address, when a cache controller determines that the cache transaction is selected for monitoring, the cache controller retrieves a pointer stored in a register, determines a location in a log memory from the pointer, and writes a transaction identifier to the determined location in the log memory. The transaction identifier is associated with the transaction address and may be a virtual address, for example. The pointer is updated and stored to the register. The architect of the apparatus may include a mechanism for atomically combining data access instructions with an instruction to commence monitoring.Type: ApplicationFiled: May 21, 2019Publication date: November 26, 2020Applicant: Arm LimitedInventors: Curtis Glenn Dunham, Jonathan Curtis Beard, Pavel Shamis, Eric Ola Harald Liljedahl
-
Publication number: 20200371913Abstract: A data processing system includes a processor, a memory system, a cache controller and a cache accessible by the processor via the cache controller. The cache controller provides an asynchronous interface between the processor and the memory system. Instructions, issued by the processor to the cache controller, are completed by the cache controller without blocking the processor. In addition, the cache controller tracks a completion status of the memory operation associated with each instruction and enables the completion status to be queried by the processor. Status of the memory operation may be recorded as an entry in a log, where the log, or a property of the log, is accessible by the processor.Type: ApplicationFiled: May 21, 2019Publication date: November 26, 2020Applicant: Arm LimitedInventors: Curtis Glenn Dunham, Pavel Shamis
-
Patent number: 10733106Abstract: A method and apparatus are provided for automatic routing of messages in a data processing system. An incoming message at an input/output (I/O) interface of the data processing system includes a message identifier and payload data. Match information, including an indicator or whether the message identifier of the incoming message matches an identifier of a request in a receive queue (RQ), is used to determine a destination for the incoming message. The incoming message is forwarded to the determined destination. Information, such as payload size and RQ position, may be used to determine allocation of the payload within a cache or cache hierarchy.Type: GrantFiled: November 2, 2017Date of Patent: August 4, 2020Assignee: ARM LTDInventors: Pavel Shamis, Alejandro Rico Carro
-
Patent number: 10664419Abstract: A method and apparatus are provided for assigning transport priorities to messages in a data processing system. An incoming message at an input/output (I/O) interface of the data processing system includes a message identifier and payload data. Match information, including an indicator or whether the message identifier of the incoming message matches an identifier of a request in a receive queue (RQ), is used to assign a transport priority value to the incoming message. The incoming message is transported to the destination node through an interconnect structure dependent upon the assigned transport priority value.Type: GrantFiled: January 29, 2018Date of Patent: May 26, 2020Assignee: Arm LimitedInventors: Alejandro Rico Carro, Pavel Shamis, Stephan Diestelhorst
-
Publication number: 20200162549Abstract: Briefly, example methods, apparatuses, and/or articles of manufacture are disclosed that may be implemented, in whole or in part, using one or more mobile communication devices and/or processing devices to facilitate and/or support one or more operations and/or techniques for executing distributed memory operations. In particular, some embodiments are directed to techniques for the traversal of vertices of a data structure maintained in a distributed memory system.Type: ApplicationFiled: November 16, 2018Publication date: May 21, 2020Inventors: Pavel Shamis, Alejandro Rico Carro
-
Patent number: 10649684Abstract: An apparatus has a monitoring data store for storing monitoring data indicating regions of a memory address space to be monitored for changes, which can include at least two non-contiguous regions. Processing circuitry updates the monitoring data in response to an update monitor instruction. Monitoring circuitry monitors accesses to the memory system and provides a notification to the processing circuitry when data associated with one of the monitored regions has changed. This improves performance and energy efficiency by reducing the overhead of polling changes to multiple regions.Type: GrantFiled: March 16, 2017Date of Patent: May 12, 2020Assignee: ARM LimitedInventors: Geoffrey Wyman Blake, Pavel Shamis
-
Publication number: 20200057640Abstract: A system, apparatus and method for ordering a sequence of processing transactions. The method includes accessing, from a memory, a program sequence of operations that are to be executed. Instructions are received, some of them having an identifier, or mnemonic, that is used to distinguish those identified operations from other operations that do not have an identifier, or mnemonic. The mnemonic indicates a distribution of the execution of the program sequence of operations. The program sequence of operations is grouped based on the mnemonic such that certain operations are separated from other operations.Type: ApplicationFiled: August 16, 2018Publication date: February 20, 2020Applicant: Arm LimitedInventors: Curtis Glenn DUNHAM, Pavel SHAMIS, Jamshed JALAL, Michael FILIPPO
-
Publication number: 20190129857Abstract: A method and apparatus are provided for automatic routing of messages in a data processing system. An incoming message at an input/output (I/O) interface of the data processing system includes a message identifier and payload data. Match information, including an indicator or whether the message identifier of the incoming message matches an identifier of a request in a receive queue (RQ), is used to determine a destination for the incoming message. The incoming message is forwarded to the determined destination. Information, such as payload size and RQ position, may be used to determine allocation of the payload within a cache or cache hierarchy.Type: ApplicationFiled: November 2, 2017Publication date: May 2, 2019Applicant: ARM LTDInventors: Pavel Shamis, Alejandro Rico Carro
-
Publication number: 20190129871Abstract: A method and apparatus are provided for assigning transport priorities to messages in a data processing system. An incoming message at an input/output (I/O) interface of the data processing system includes a message identifier and payload data. Match information, including an indicator or whether the message identifier of the incoming message matches an identifier of a request in a receive queue (RQ), is used to assign a transport priority value to the incoming message. The incoming message is transported to the destination node through an interconnect structure dependent upon the assigned transport priority value.Type: ApplicationFiled: January 29, 2018Publication date: May 2, 2019Applicant: Arm LimitedInventors: Alejandro Rico Carro, Pavel Shamis, Stephan Diestelhorst
-
Publication number: 20180267741Abstract: An apparatus has a monitoring data store for storing monitoring data indicating regions of a memory address space to be monitored for changes, which can include at least two non-contiguous regions. Processing circuitry updates the monitoring data in response to an update monitor instruction. Monitoring circuitry monitors accesses to the memory system and provides a notification to the processing circuitry when data associated with one of the monitored regions has changed. This improves performance and energy efficiency by reducing the overhead of polling changes to multiple regions.Type: ApplicationFiled: March 16, 2017Publication date: September 20, 2018Inventors: Geoffrey Wyman BLAKE, Pavel SHAMIS
-
Patent number: 9344490Abstract: A Network Interface (NI) includes a host interface, which is configured to receive from a host processor of a node one or more cross-channel work requests that are derived from an operation to be executed by the node. The NI includes a plurality of work queues for carrying out transport channels to one or more peer nodes over a network. The NI further includes control circuitry, which is configured to accept the cross-channel work requests via the host interface, and to execute the cross-channel work requests using the work queues by controlling an advance of at least a given work queue according to an advancing condition, which depends on a completion status of one or more other work queues, so as to carry out the operation.Type: GrantFiled: July 7, 2014Date of Patent: May 17, 2016Assignee: Mellanox Technologies Ltd.Inventors: Noam Bloch, Gil Bloch, Ariel Shachar, Hillel Chapman, Ishai Rabinobitz, Pavel Shamis, Gilad Shainer
-
Publication number: 20140324939Abstract: A Network Interface (NI) includes a host interface, which is configured to receive from a host processor of a node one or more cross-channel work requests that are derived from an operation to be executed by the node. The NI includes a plurality of work queues for carrying out transport channels to one or more peer nodes over a network. The NI further includes control circuitry, which is configured to accept the cross-channel work requests via the host interface, and to execute the cross-channel work requests using the work queues by controlling an advance of at least a given work queue according to an advancing condition, which depends on a completion status of one or more other work queues, so as to carry out the operation.Type: ApplicationFiled: July 7, 2014Publication date: October 30, 2014Inventors: Noam Bloch, Gil Bloch, Ariel Shachar, Hillel Chapman, Ishai Rabinobitz, Pavel Shamis, Gilad Shainer
-
Patent number: 8811417Abstract: A Network Interface (NI) includes a host interface, which is configured to receive from a host processor of a node one or more cross-channel work requests that are derived from an operation to be executed by the node. The NI includes a plurality of work queues for carrying out transport channels to one or more peer nodes over a network. The NI further includes control circuitry, which is configured to accept the cross-channel work requests via the host interface, and to execute the cross-channel work requests using the work queues by controlling an advance of at least a given work queue according to an advancing condition, which depends on a completion status of one or more other work queues, so as to carry out the operation.Type: GrantFiled: November 15, 2010Date of Patent: August 19, 2014Assignee: Mellanox Technologies Ltd.Inventors: Noam Bloch, Gil Bloch, Ariel Shachar, Hillel Chapman, Ishai Rabinovitz, Pavel Shamis, Gilad Shainer