Abstract: Convolutional neural network compilers for programmable functional array processors are provided. One such compiler involves a method for fitting a convolutional neural network (CNN) to a CNN processor to be performed by a compiler, the method comprising: receiving a CNN; converting the CNN into a CNN graph; converting the CNN graph into a memory graph comprising graph primitives corresponding to a plurality of components of the CNN processor including a primary memory; performing a memory analysis to determine an amount of memory required in the primary memory for at least one of the graph primitives; identifying a plurality of tokens within the memory graph to form a token graph, each of the plurality of tokens comprising one or more of the graph primitives; and generating, using the plurality of identified tokens, configuration settings for each of the plurality of components of the CNN processor.

Abstract: Systems and methods for performing direct conversion of image sensor data to image analytics are provided. One such system for directly processing sensor image data includes a sensor configured to capture an image and generate corresponding image data in a raw Bayer format, and a convolution neural network (CNN) coupled to the sensor and configured to generate image analytics directly from the image data in the raw Bayer format. Systems and methods for training the CNN are provided, and may include a generative model that is configured to convert RGB images into estimated images in the raw Bayer format.

Abstract: Systems and methods for performing direct conversion of image sensor data to image analytics are provided. One such system for directly processing sensor image data includes a sensor configured to capture an image and generate corresponding image data in a raw Bayer format, and a convolution neural network (CNN) coupled to the sensor and configured to generate image analytics directly from the image data in the raw Bayer format. Systems and methods for training the CNN are provided, and may include a generative model that is configured to convert RGB images into estimated images in the raw Bayer format.

Abstract: Convolutional neural network compilers for programmable functional array processors are provided. One such compiler involves a method for fitting a convolutional neural network (CNN) to a CNN processor to be performed by a compiler, the method comprising: receiving a CNN; converting the CNN into a CNN graph; converting the CNN graph into a memory graph comprising graph primitives corresponding to a plurality of components of the CNN processor including a primary memory; performing a memory analysis to determine an amount of memory required in the primary memory for at least one of the graph primitives; identifying a plurality of tokens within the memory graph to form a token graph, each of the plurality of tokens comprising one or more of the graph primitives; and generating, using the plurality of identified tokens, configuration settings for each of the plurality of components of the CNN processor.

Abstract: Efficient communication between processing elements of a configurable processor for implementing CNNs are provided. One such configurable processor includes a first processing element coupled to an image sensor, and a second processing element coupled to the first processing element via a serial communication link. The first processing element is configured to generate preselected data to be communicated using the serial communication link, receive image data from the image sensor, the image data including a first image data including multiple rows of data, send, via the serial communication link, a first row of the first image data to the second processing element, send, via the serial communication link, a portion of the preselected data to the second processing element, and send, via the serial communication link, a second row of the first image data to the second processing element.

Abstract: Systems and methods for secure face authentication are provided. One such system is embodied as a first device for authenticating a user using facial recognition for a second device, the first device including a memory; and a processing circuitry coupled to the memory, the second device, and a camera, where the processing circuitry is configured to: receive a reference facial image of the user from the second device; receive a first facial image of the user from the camera; perform facial recognition using the first facial image and the reference facial image; and send an indication to the second device indicative of whether the first facial image was a match for the reference facial image; and where the first device is configured to operate without an operating system.

Abstract: Machine learning architectures configured to perform pattern recognition using a structurally regularized convolutional neural network architecture, along with corresponding methods of operation, are provided. One such architecture includes a memory, and a processor coupled to the memory and configured to: receive data comprising a pattern to be recognized, decompose the data into a plurality of sub-bands, process each of the plurality of sub-bands with a respective convolutional neural network (CNN) to generate a plurality of outputs, where each of the CNNs operates independently of the other CNNs, aggregate the outputs of the CNNs, and train, using the aggregated output, the CNNs to recognize the pattern.

Abstract: Systems and methods for performing direct conversion of image sensor data to image analytics are provided. One such system for directly processing sensor image data includes a sensor configured to capture an image and generate corresponding image data in a raw Bayer format, and a convolution neural network (CNN) coupled to the sensor and configured to generate image analytics directly from the image data in the raw Bayer format. Systems and methods for training the CNN are provided, and may include a generative model that is configured to convert RGB images into estimated images in the raw Bayer format.

Abstract: Configurable processors for implementing CNNs are provided. One such configurable CNN processor includes a plurality of core compute circuitry elements, each configured to perform a CNN function in accordance with a preselected dataflow graph, an active memory buffer, a plurality of connections between the active memory buffer and the plurality of core compute circuitry elements, each established in accordance with the preselected dataflow graph, a plurality of connections between the plurality of core compute circuitry elements, each established in accordance with the preselected dataflow graph, wherein the active memory buffer is configured to move data between the plurality of core compute circuitry elements via the active memory buffer in accordance with the preselected dataflow graph.

Abstract: Systems and methods for decoding compressed data are described herein. A memory may receive a data stream comprising a string of encoded symbols encoded using an arithmetic coding based coding technique. The string of encoded symbols represents a series of one or more decoded symbols. Each of the one or more decoded symbols comprises one of a most probable symbol and a least probable symbol. A processor may determine a number of consecutive most probable symbols in the series of one or more decoded symbols by performing a plurality of parallel mathematical comparisons based on one or more of the encoded symbols. The processor may further decode a group of symbols of the series of one or more decoded symbols based on the plurality of parallel mathematical comparisons. The group of symbols comprises the number of consecutive most probable symbols.

Abstract: Systems and methods for decoding compressed data are described herein. A memory may receive a data stream comprising a string of encoded symbols encoded using an arithmetic coding based coding technique. The string of encoded symbols represents a series of one or more decoded symbols. Each of the one or more decoded symbols comprises one of a most probable symbol and a least probable symbol. A processor may determine a number of consecutive most probable symbols in the series of one or more decoded symbols by performing a plurality of parallel mathematical comparisons based on one or more of the encoded symbols. The processor may further decode a group of symbols of the series of one or more decoded symbols based on the plurality of parallel mathematical comparisons. The group of symbols comprises the number of consecutive most probable symbols.

Abstract: This disclosure provides systems, methods and apparatus for a display device incorporating high-speed data links. A display device can include a controller and a plurality of driver integrated circuits (ICs) for driving portions of a display panel. The controller can communicate data and control signals with the plurality of driver ICs over a plurality of links. The controller can adjust power consumed for communication over one link independently of the power consumed for communication over other links. The controller can adjust power consumed by the controller and a driver IC, as well as transmitter and receiver parameters to provide an acceptable quality of data transmission over the corresponding link. The controller can adjust the power consumed by adjusting a voltage swing of one or more transmission amplifiers and/or controlling the current supplied to receiver amplifiers of the driver ICs.

Abstract: A processor includes a triple-base-number-system (TBNS) Arithmetic Unit architecture. TBNS processing enables extremely high-performance digital signal processing of larger word-size data, and enables a processor architecture having reduced hardware complexity and power dissipation. With demanding signal processing applications a TBNS processing is much more efficient as compared to either traditional SBNS or even DBNS. In a processor, a Multiplication Unit comprises at least three Adders to each add an extracted pair of like powers of two numbers to be multiplied. A result of one Adder controls a number of bits of shift of a barrel shifter, and a result of remaining Adders are input to a lookup table feeding the barrel shifter. A register holds an output of the barrel shifter. TBNS processing system includes a binary-to-TBNS data converter adapting a Binary-Search-Tree and Range Table to convert binary data/numbers into TBNS representation.