Patents by Inventor Pavlos Mattheakis

Pavlos Mattheakis has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8074193
    Abstract: A computer readable storage medium includes executable instructions to receive a specification of a combinational logic circuit. The specification of the combinational logic circuit is converted to a Single-Rail un-encoded circuit and a Dual-Rail encoded circuit, which periodically encodes a null value, a first valid state and a second valid state on two wires. A logic operation of the Single-Rail un-encoded circuit transpires during processing of a null value by the Dual-Rail encoded circuit.
    Type: Grant
    Filed: March 11, 2009
    Date of Patent: December 6, 2011
    Assignee: Institute of Computer Science (ICS) of the Foundation for Research & Technology Hellas-Foundation for Research and Technology Hellas (FORTH)
    Inventors: Christos P. Sotiriou, Pavlos Mattheakis, Michail Christofilopoulos
  • Publication number: 20100231261
    Abstract: A computer readable storage medium includes executable instructions to receive a specification of a combinational logic circuit. The specification of the combinational logic circuit is converted to a Single-Rail un-encoded circuit and a Dual-Rail encoded circuit, which periodically encodes a null value, a first valid state and a second valid state on two wires. A logic operation of the Single-Rail un-encoded circuit transpires during processing of a null value by the Dual-Rail encoded circuit.
    Type: Application
    Filed: March 11, 2009
    Publication date: September 16, 2010
    Inventors: Christos P. Sotiriou, Pavlos Mattheakis, Michail Christofilopoulos
  • Patent number: 7603635
    Abstract: A computer readable storage medium includes executable instructions to analyze an asynchronous, multi-rail digital circuit to identify a gating sub-circuit and a gated sub-circuit. The asynchronous, multi-rail digital circuit is transformed to segregate the gating sub-circuit and the gated sub-circuit.
    Type: Grant
    Filed: July 31, 2007
    Date of Patent: October 13, 2009
    Assignee: Institute of Computer Science (ICS) of the Foundation for Research & Technology Hellas, Foundation for Research and Technology Hellas (Forth)
    Inventors: Christos P. Sotiriou, Pavlos Mattheakis