Abstract: A dielectric ceramic composition, a method for producing a dieelctric composition and the use of the dielectric composition are disclosed. In an embodiment a ceramic composition includes a main component with a quantity ratio Mg(1+x)(1?y)O3+xA(1+x)ySi(1?z)Dz and a remainder comprising contaminants, wherein 0.01×0.30, wherein 0.00?y?0.20, and wherein 0.00?z?1.00.

Abstract: Doped, low-temperature co-fired ceramic (LTCC) insulating substrates and related wiring boards and methods of manufacture are disclosed. The doped, LTCC insulating substrate is formed from a baked (e.g., sintered) glass-ceramic aggregate material formed from a glass material, a ceramic filler material, and a composite oxide. The crystallized glass-ceramic aggregate is then doped with Iron and/or Manganese before baking. Iron or Manganese can further reduce dielectric loss and the loss tangent of the LTCC insulating substrate formed from that glass material. The glass material becomes crystallized due to an oxide crystal phase being deposited on the glass material during baking, which reduces the dielectric losses. This may be important for the application use as wiring boards for high radio-frequency (RF) electrical circuits where low dielectric loss and loss tangent is desired to achieve a desired signal transmission delay performance.

Abstract: Doped, low-temperature co-fired ceramic (LTCC) insulating substrates and related wiring boards and methods of manufacture are disclosed. The doped, LTCC insulating substrate is formed from a baked (e.g., sintered) glass-ceramic aggregate material formed from a glass material, a ceramic filler material, and a composite oxide. The crystallized glass-ceramic aggregate is then doped with Iron and/or Manganese before baking. Iron or Manganese can further reduce dielectric loss and the loss tangent of the LTCC insulating substrate formed from that glass material. The glass material becomes crystallized due to an oxide crystal phase being deposited on the glass material during baking, which reduces the dielectric losses. This may be important for the application use as wiring boards for high radio-frequency (RF) electrical circuits where low dielectric loss and loss tangent is desired to achieve a desired signal transmission delay performance.

Abstract: An overvoltage protection element and a method for producing an overvoltage protection element is disclosed. In an embodiment, the overvoltage protection element includes a first electrode, a second electrode and a discharge region arranged between the first electrode and the second electrode, wherein a porous discharge dielectric is arranged in the discharge region, and wherein the overvoltage protection element is configured to discharge a gas in pores of the discharge dielectric and produce an electrically conductive connection between the first electrode and the second electrode.

Abstract: A dielectric ceramic composition, a method for producing a dieelctric composition and the use of the dielectric composition are disclosed. In an embodiment a ceramic composition includes a main component with a quantity ratio Mg(1+x)(1?y)O3+xA(1+x)ySi(1?z)Dz and a remainder comprising contaminants, wherein 0.01×0.30, wherein 0.00?y?0.20, and wherein 0.00?z?1.00.

Abstract: A chip and a method for manufacturing a chip are disclosed. In an embodiment, the chip includes a varistor layer composed of zinc oxide, a multilayered electrode structure which realizes a varistor function in the varistor layer and at least two solderable or bondable external contacts on a first main surface of the varistor layer. The chip further includes a glass layer disposed on the first main surface leaving only the external contacts uncovered, wherein the glass layer includes, as main constituents, oxides of Si and/or Ge, B and K, which in total have at least 70% by weight of the constituents of the glass layer, and wherein the glass layer is substantially free of Al, Ga, Cr and Ti.

Abstract: For a carrier plate, it is proposed to brace a first ceramic functional layer over a connecting layer (VS) with a ceramic stressing layer (SPS) in order to reduce the lateral sintering shrinkage. The functional layer (FS) and the stressing layer (SPS) are glass-free or have only a small glass content of less than 5 wt %, whereas the connecting layer (VS) comprises a glass component or is a glass layer.

Abstract: A film stack made from compacted green films and capable of being sintered to form a ceramic component with monolithic multi-layer structure is disclosed. The film stack includes a functional layer comprising a green film comprising a functional ceramic and a tension layer comprising a green film comprising a dielectric material. The tension layer is directly adjacent to the functional layer in the multi-layer structure. The multilayer structure also includes a first metallization plane and second metallization plane. The functional layer is between the first metallization plane and the second metallization plane.

Abstract: A chip and a method for manufacturing a chip are disclosed. In an embodiment, the chip includes a varistor layer composed of zinc oxide, a multilayered electrode structure which realizes a varistor function in the varistor layer and at least two solderable or bondable external contacts on a first main surface of the varistor layer. The chip further includes a glass layer disposed on the first main surface leaving only the external contacts uncovered, wherein the glass layer includes, as main constituents, oxides of Si and/or Ge, B and K, which in total have at least 70% by weight of the constituents of the glass layer, and wherein the glass layer is substantially free of Al, Ga, Cr and Ti.

Abstract: A film stack made from compacted green films and capable of being sintered to form a ceramic component with monolithic multi-layer structure is disclosed. The film stack includes a functional layer comprising a green film comprising a functional ceramic and a tension layer comprising a green film comprising a dielectric material. The tension layer is directly adjacent to the functional layer in the multi-layer structure. The multilayer structure also includes a first metallization plane and a second metallization plane. The functional layer is between the first metallization plane and the second metallization plane.

Abstract: An overvoltage protection element and a method for producing an overvoltage protection element is disclosed. In an embodiment, the overvoltage protection element includes a first electrode, a second electrode and a discharge region arranged between the first electrode and the second electrode, wherein a porous discharge dielectric is arranged in the discharge region, and wherein the overvoltage protection element is configured to discharge a gas in pores of the discharge dielectric and produce an electrically conductive connection between the first electrode and the second electrode.

Abstract: A multilayer component includes a dielectric ceramic material that can be co-sintered with a varistor ceramic to form a monolithic multilayer component according to the invention. The multilayer component therefore includes a layer of a varistor ceramic and another layer of a dielectric. Both layers can be arranged directly adjacent to one another in the multilayer component. In the multilayer component, metallizations are arranged on or between the ceramic layers. The metallizations are structured to form conductor sections and metallized areas. The metallizations form together with the ceramic layers alongside a varistor at least one further component selected from at least one of the component functions.

Abstract: An electrical component includes a ceramic base body. The ceramic base body includes several ceramic layers including a function layer and a composite layer bordering the function layer. The composite layer can include a zirconium oxide-glass filler mixture.

Abstract: A multilayer component includes a dielectric ceramic material that can be co-sintered with a varistor ceramic to form a monolithic multilayer component according to the invention. The multilayer component therefore includes a layer of a varistor ceramic and another layer of a dielectric. Both layers can be arranged directly adjacent to one another in the multilayer component. In the multilayer component, metallizations are arranged on or between the ceramic layers. The metallizations are structured to form conductor sections and metallized areas. The metallizations form together with the ceramic layers alongside a varistor at least one further component selected from at least one of the component functions.

Abstract: A ceramic mixed system is proposed that includes a two-phase mixture of pure components A and B, wherein phase A is based on the cubic to tetragonal modification of Bi3NbO7 and phase B is based on a monoclinic pyrochlore modification of Bi2(Zn2/3Nb4/3)O7. The electrical properties of ceramics produced therefrom make the material suitable for components having a multilayer structure in which capacitors and inductors are integrated and which can be used in data processing or signal processing.

Abstract: An electrical component includes a ceramic base body. The ceramic base body includes several ceramic layers including a function layer and a composite layer bordering the function layer. The composite layer can include a zirconium oxide-glass filler mixture.

Abstract: A ceramic mixed system is proposed that includes a two-phase mixture of pure components A and B, wherein phase A is based on the cubic to tetragonal modification of Bi3NbO7 and phase B is based on a monoclinic pyrochlore modification of Bi2(Zn2/3Nb4/3)O7. The electrical properties of ceramics produced therefrom make the material suitable for components having a multilayer structure in which capacitors and inductors are integrated and which can be used in data processing or signal processing.

Abstract: A film stack made from compacted green films and capable of being sintered to form a ceramic component with monolithic multi-layer structure is disclosed. The film stack includes a functional layer comprising a green film comprising a functional ceramic and a tension layer comprising a green film comprising a dielectric material. The tension layer is directly adjacent to the functional layer in the multi-layer structure. The multilayer structure, also includes a first metallization plane and a second metallization plane. The functional layer is between the first metallization plane and the second metallization plane.