Patents by Inventor Pawan Chhabra
Pawan Chhabra has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11494248Abstract: A warm mission-mode reset may be performed in a portable computing device. Assertion of a signal indicating an error condition may be detected. In response to detection of the signal indicating an error condition, a signal indicating a request to preserve memory contents may be provided to a DRAM subsystem. Then, in response to a signal acknowledging the DRAM subsystem is preserving the memory contents, a system reset signal may be asserted.Type: GrantFiled: December 20, 2019Date of Patent: November 8, 2022Assignee: QUALCOMM IncorporatedInventors: Rakesh Misra, Rohit Gupta, Shubham Maheshwari, Pawan Chhabra
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Publication number: 20210191795Abstract: A warm mission-mode reset may be performed in a portable computing device. Assertion of a signal indicating an error condition may be detected. In response to detection of the signal indicating an error condition, a signal indicating a request to preserve memory contents may be provided to a DRAM subsystem. Then, in response to a signal acknowledging the DRAM subsystem is preserving the memory contents, a system reset signal may be asserted.Type: ApplicationFiled: December 20, 2019Publication date: June 24, 2021Inventors: RAKESH MISRA, ROHIT GUPTA, SHUBHAM MAHESHWARI, PAWAN CHHABRA
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Patent number: 10656203Abstract: Certain aspects of the present disclosure provide an apparatus for processor core testing. The apparatus generally includes a high-speed input-output (HSIO) interface, a general purpose input-output (GPIO) interface, a multiplexer having a first input coupled to the GPIO interface, a test controller coupled between the HSIO interface and a second input of the multiplexer, and one or more processor cores coupled to the output of the multiplexer.Type: GrantFiled: February 18, 2019Date of Patent: May 19, 2020Assignee: QUALCOMM IncorporatedInventors: Punit Kishore, Jais Abraham, Pawan Chhabra
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Publication number: 20200058330Abstract: Systems and methods are disclosed for providing micro-idle memory power management. One embodiment of a method comprises receiving and storing an exit latency vote from each of a plurality of memory subsystems on a system on chip electrically coupled to a system memory. In response to a micro-idle memory state in which each of the memory subsystems are idle, a minimum exit latency value from the plurality of exit latency votes is determined. One of a plurality of system memory modes is selected which has a micro-idle sleep time that meets the minimum exit latency value while minimizing system memory power consumption. The selected system memory mode is initiated.Type: ApplicationFiled: August 14, 2018Publication date: February 20, 2020Inventors: PAWAN CHHABRA, VENKATA DEVARASETTY, MAYANK GUPTA, MAHESHWAR THAKUR SINGH, HARSHIT TIWARI
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Patent number: 10359833Abstract: A hardware system is disclosed for active-core-based performance boost. In an example aspect, the hardware system includes multiple cores and a power mode manager. Each core can be powered up if active or powered down if inactive. The power mode manager manages a power mode collection including an independent power mode collection and an active-core-dependent power mode collection. The power mode manager includes a software-accessible power mode manager and a hardware-reserved power mode manager. The software-accessible power mode manager provides a power-mode-triggering pathway to enable software to trigger activation of an independent power mode of the independent power mode collection. The hardware-reserved power mode manager excludes the software from being able to trigger activation of a dependent power mode of the active-core-dependent power mode collection and triggers activation of a dependent power mode of the active-core-dependent collection based on a number of active cores of the multiple cores.Type: GrantFiled: June 20, 2016Date of Patent: July 23, 2019Assignee: QUALCOMM IncorporatedInventors: Sarbartha Banerjee, Pawan Chhabra, Navid Toosizadeh, Sreekanth Nallagatla, Shih-Hsin Jason Hu
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Publication number: 20170364140Abstract: A hardware system is disclosed for active-core-based performance boost. In an example aspect, the hardware system includes multiple cores and a power mode manager. Each core can be powered up if active or powered down if inactive. The power mode manager manages a power mode collection including an independent power mode collection and an active-core-dependent power mode collection. The power mode manager includes a software-accessible power mode manager and a hardware-reserved power mode manager. The software-accessible power mode manager provides a power-mode-triggering pathway to enable software to trigger activation of an independent power mode of the independent power mode collection. The hardware-reserved power mode manager excludes the software from being able to trigger activation of a dependent power mode of the active-core-dependent power mode collection and triggers activation of a dependent power mode of the active-core-dependent collection based on a number of active cores of the multiple cores.Type: ApplicationFiled: June 20, 2016Publication date: December 21, 2017Inventors: Sarbartha Banerjee, Pawan Chhabra, Navid Toosizadeh, Sreekanth Nallagatla, Shih-Hsin Jason Hu
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Publication number: 20170269984Abstract: Systems and methods are disclosed for improved processor hang detection. An exemplary method comprises setting a timer with a hang threshold value for each of a plurality of processors of a system on a chip (SoC). The hang threshold value represents a time in microseconds. The method further comprising receiving a first heartbeat signal from each of the plurality of processors with detection logic hardware of a hang controller coupled to the plurality of processors and to the timer. The timer is reset for each of the plurality of processors if a second heartbeat signal is received from the corresponding one of the plurality of processors before the timer expires. Alternatively, a hang event notification is generated if the second heartbeat signal is not received from the corresponding one of the plurality of processors before the timer expires.Type: ApplicationFiled: March 18, 2016Publication date: September 21, 2017Inventors: ANANTHA IDAPALAPATI, AJAYKUMAR SHANKARGOUDA PATIL, SUBODH SINGH, RAMSWAROOP SOMANI, GOPI KRISHNA NEDANURI, PAWAN CHHABRA, SARBARTHA BANERJEE, VICTOR WONG
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Publication number: 20150161057Abstract: Systems and methods are disclosed for providing memory address translation for a memory management system. One embodiment of such a system comprises a memory device and an application processor in communication via a system interconnect. The application processor comprises test code for testing one or more of a plurality of hardware devices. Each of the hardware devices has a corresponding system memory management unit (SMMU) for processing memory requests associated with the hardware device to the memory device. The system further comprises a client-side address translation system in communication with the system interconnect and the plurality of SMMUs. The client-side address translation system is configured to selectively route stimulus traffic associated with the test code to a client port on one or more of the plurality of SMMUs for testing the corresponding hardware devices.Type: ApplicationFiled: January 5, 2014Publication date: June 11, 2015Applicant: Qualcomm IncorporatedInventors: THOMAS M. ZENG, AZZEDINE TOUZNI, STEPHEN A. MOLLOY, SATYAKI MUKHERJEE, ABHIRAMI SENTHILKUMARAN, OLAV HAUGAN, TZUNG REN TZENG, TAREK ZGHAL, JEAN-LOUIS O. TARDIEUX, AJAY UPADHYAYA, ZHURANG ZHAO, PAWAN CHHABRA, SUBRAHMANYAM MOOLA, PAVAN KUMAR, JAYDEEP R. CHOKSHI, VICTOR K. WONG, VIPUL C. GANDHI
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Patent number: 8869099Abstract: A method and system for enabling multi-tenancy for software as a service application is provided. The method includes defining a plurality of policy configuration files for each tenant of the SaaS application. The method further includes identifying a tenant and tenant-context for the SaaS application. Thereafter, the method includes identifying one or more policy configuration files and then applying one or more variations to one or more variation points to provide the SaaS application to the user.Type: GrantFiled: July 28, 2009Date of Patent: October 21, 2014Assignee: Infosys LimitedInventors: Chetan Jagatkishore Kothari, Pawan Chhabra
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Publication number: 20130007591Abstract: A system and computer-implemented method for creating one or more e-commerce websites in real-time is provided. The methodology for creating one or more e-commerce websites in real-time comprises receiving, via a user interface on a computing device, request to access a tenant's website. The methodology further comprises identifying, using a computer system, a tenant corresponding to the received request. Further, the methodology comprises associating, using the computer system, one or more e-commerce applications, corresponding to the identified tenant, to the tenant's website. The methodology also comprises applying, using the computer system, one or more predetermined changes to the tenant's website corresponding to one or more predefined policies for generating the e-commerce website.Type: ApplicationFiled: September 20, 2011Publication date: January 3, 2013Applicant: INFOSYS LIMITEDInventors: Chetan Jagatkishore Kothari, Pawan Chhabra
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Publication number: 20100023937Abstract: A method and system for enabling multi-tenancy for software as a service application is provided. The method includes defining a plurality of policy configuration files for each tenant of the SaaS application. The method further includes identifying a tenant and tenant-context for the SaaS application. Thereafter, the method includes identifying one or more policy configuration files and then applying one or more variations to one or more variation points to provide the SaaS application to the user.Type: ApplicationFiled: July 28, 2009Publication date: January 28, 2010Inventors: Chetan Jagatkishore Kothari, Pawan Chhabra
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Patent number: 7475314Abstract: In one embodiment, a method for on-die read only memory (ROM) built-in self-test (BIST) is disclosed. The method comprises testing odd word line entries of a read-only memory (ROM) array by performing two passes through the ROM array to test each odd word line entry for static and delay faults, testing even word line entries of the ROM array by performing two passes through the ROM array to test each even word line entry for static and delay faults, and testing each entry of the ROM array for static faults masked by dynamic faults by performing two passes through the ROM array. Other embodiments are also described.Type: GrantFiled: June 8, 2006Date of Patent: January 6, 2009Assignee: Intel CorporationInventors: Pawan Chhabra, Tessil Thomas
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Publication number: 20070143650Abstract: In one embodiment, a method for on-die read only memory (ROM) built-in self-test (BIST) is disclosed. The method comprises testing odd word line entries of a read-only memory (ROM) array by performing two passes through the ROM array to test each odd word line entry for static and delay faults, testing even word line entries of the ROM array by performing two passes through the ROM array to test each even word line entry for static and delay faults, and testing each entry of the ROM array for static faults masked by dynamic faults by performing two passes through the ROM array. Other embodiments are also described.Type: ApplicationFiled: June 8, 2006Publication date: June 21, 2007Inventors: Pawan Chhabra, Tessil Thomas