Patents by Inventor Pawan Deep Gandhi

Pawan Deep Gandhi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Using smart timing models for gate level timing simulation
    Patent number: 9710579
    Abstract: A system and method for simulating the timing of an integrated circuit design using abstract timing models. An abstract or smart timing model is created as a model of a design component or block having partial timing that includes the timing for the boundary or interface logic but removes timing for internal registers. The smart timing model may additionally preserve the timing for asynchronous or multi-cycle paths, or add interconnect delays for certain internal elements, to ensure accurate timing.
    Type: Grant
    Filed: December 2, 2013
    Date of Patent: July 18, 2017
    Assignee: Cadence Design Systems, Inc.
    Inventors: Gagandeep Singh, Pawan Deep Gandhi
  • System for testing integrated circuit with asynchronous clock domains
    Patent number: 8464117
    Abstract: A system for scan testing various clock domains of an integrated circuit includes a clock gate control unit and clock gating cells. The clock gating cells receive a single test clock signal provided externally through one package pin of the integrated circuit. The clock gate control unit provides clock gate control signals to the clock gating cells. The clock gating cells generate time-staggered clock signals based on the clock gate control signals.
    Type: Grant
    Filed: May 25, 2010
    Date of Patent: June 11, 2013
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Shruti Rakheja, Sunny Arora, Pawan Deep Gandhi, Rashmi Moudgil
  • SYSTEM FOR TESTING INTEGRATED CIRCUIT WITH ASYNCHRONOUS CLOCK DOMAINS
    Publication number: 20110296265
    Abstract: A system for scan testing various clock domains of an integrated circuit includes a clock gate control unit and clock gating cells. The clock gating cells receive a single test clock signal provided externally through one package pin of the integrated circuit. The clock gate control unit provides clock gate control signals to the clock gating cells. The clock gating cells generate time-staggered clock signals based on the clock gate control signals.
    Type: Application
    Filed: May 25, 2010
    Publication date: December 1, 2011
    Applicant: FREESCALE SEMICONDUCTOR, INC
    Inventors: Shruti RAKHEJA, Sunny Arora, Pawan Deep Gandhi, Rashmi Moudgil