Abstract: Described is a system for discovering and configuring backup settings for protectable storage assets of a storage array. The system may perform such discovery and configuration for a storage array by providing an efficient centralized management capability. In addition, the centralized management capability allows for the creation of backup policies that are host-aware. Accordingly, the system may account for the interrelationship between storage devices, storage groups, and host devices to prevent potential inconsistencies and conflicts that may arise when creating a centralized backup policy.

Abstract: Described is a system for discovering and configuring backup settings for protectable storage assets of a storage array. The system may perform such discovery and configuration for a storage array by providing an efficient centralized management capability. In addition, the centralized management capability allows for the creation of backup policies that are host-aware. Accordingly, the system may account for the interrelationship between storage devices, storage groups, and host devices to prevent potential inconsistencies and conflicts that may arise when creating a centralized backup policy.

Abstract: Snapshot capability-aware discovery of tagged application resources is described. A backup server inputs an identifier of an application's resource from the application's host. If the backup server determines that the application resource identifier was input with a snapshot capable tag, and that the application's resource satisfies any of the snapshot policy rules, the backup server identifies the data protection policy for the satisfied snapshot policy rule. The backup server outputs a request to the application's host to use the identified data protection policy to create a snapshot of the application's resource that was input with any associated snapshot capable tag.

Abstract: Creating vendor-neutral data protection operations for vendors' application resources is described. Capabilities specified for data protection operations by a vendor of an application are input from a host of the application. Any capabilities specified for the data protection operations are used to create a vendor-neutral version of a data protection operation for a resource of the application. The vendor-neutral version of the data protection operation for the application resource is output to the host. A result of performing the vendor-neutral version of the data protection operation on the application resource is input from the host.

Abstract: Vendor-neutral models of vendors' application resources are described. A host outputs capabilities of data protection operations which are specified by a vendor of an application that is installed on the host. The host inputs a vendor-neutral version of a data protection operation, based on any of the capabilities, for a resource of the application. The host uses a vendor-neutral model of the resource of the application to perform the vendor-neutral version of the data protection operation on the application resource.

Abstract: Tagging application resources for snapshot capability-aware discovery is described. If an application's host determines that one of an application's resource satisfies any snapshot capability rule, the application's host associates the application resource with a snapshot capable tag. The application's host outputs an identifier of the application resource and any associated snapshot capable tag to a backup server. The application's host inputs a request from the backup server to create a snapshot of the application resource associated with the snapshot capable tag and creates the snapshot of the application resource associated with the snapshot capable tag.

Abstract: Server resource-aware discovery of client application resources is described. A server requests for clients to discover their application resources. If a utilization of a server resource does not exceed a server resource utilization threshold, the server fetches a copy of a client application resource from a client at a fetch rate. If the utilization of the server resource exceeds the server resource utilization threshold, the server fetches the copy of the client application resource from the client at a lesser fetch rate.

Abstract: Techniques for suppression of program disturb in flash memory devices are described herein. In an example embodiment, a method for suppression of program disturb in a flash memory array is provided. The flash memory array comprises rows and columns of memory cells, where the memory cells in each row are coupled to a source line and to a select-gate (SG) line, and the memory cells in each column are coupled to a respective bit line (BL). During a program memory operation, a first voltage, of a selected SG line, and a second voltage, of an unselected BL, are regulated independently of a power supply voltage of the flash memory array, where the first voltage is regulated in a first range of 0.9V to 1.1V and the second voltage is regulated in a second range of 0.4V to 1.2V.

Abstract: Systems, methods, and devices include counters configured to implement count operations. Systems include non-volatile memory devices which include a first counter configured to store a first plurality of data values representing a plurality of count operations, and a second counter configured to store a second plurality of data values representing a number of erase operations applied to the first counter. Systems further include control circuitry configured to implement read, write, and erase operations for the first counter and the second counter, determine a partial count value based, at least in part, on a current value of the second counter and at least one physical parameter of the first counter, and generate a count value by adding the partial count value with a current value of the first counter. Such counters and control circuitry are immune data loss due to power loss events.

Abstract: Techniques for suppression of program disturb in flash memory devices are described herein. In an example embodiment, a method for suppression of program disturb in a flash memory array is provided. The flash memory array comprises rows and columns of memory cells, where the memory cells in each row are coupled to a source line and to a select-gate (SG) line, and the memory cells in each column are coupled to a respective bit line (BL). During a program memory operation, a first voltage, of a selected SG line, and a second voltage, of an unselected BL, are regulated independently of a power supply voltage of the flash memory array, where the first voltage is regulated in a first range of 0.9V to 1.1V and the second voltage is regulated in a second range of 0.4V to 1.2V.

Abstract: Techniques for suppression of program disturb in flash memory devices are described herein. In an example embodiment, a method for suppression of program disturb in a flash memory array is provided. The flash memory array comprises rows and columns of memory cells, where the memory cells in each row are coupled to a source line and to a select-gate (SG) line, and the memory cells in each column are coupled to a respective bit line (BL). During a program memory operation, a first voltage, of a selected SG line, and a second voltage, of an unselected BL, are regulated independently of a power supply voltage of the flash memory array, where the first voltage is regulated in a first range of 0.9V to 1.1V and the second voltage is regulated in a second range of 0.4V to 1.2V.

Abstract: A non-volatile memory device and methods for operating the same are provided. The memory device may have multiple complementary memory cells. The method of blank check includes detecting a state value of each of the true and complementary transistors, generating an upper state value, Wherein a first predetermined amount of the true and complementary transistors have greater state values than the upper state value, generating a lower state value, wherein a second predetermined amount of the true and complementary transistors have less state values than the lower state value, generating a state value range based on a difference between the upper state value and the lower state value, and comparing the state value range to a threshold value to determine whether the plurality of complementary memory cells is in a blank state or a non-blank state. Other embodiments are also disclosed herein.

Abstract: Techniques for suppression of program disturb in flash memory devices are described herein. In an example embodiment, a method for suppression of program disturb in a flash memory array is provided. The flash memory array comprises rows and columns of memory cells, where the memory cells in each row are coupled to a source line and to a select-gate (SG) line, and the memory cells in each column are coupled to a respective bit line (BL). During a program memory operation, a first voltage, of a selected SG line, and a second voltage, of an unselected BL, are regulated independently of a power supply voltage of the flash memory array, where the first voltage is regulated in a first range of 0.9V to 1.1V and the second voltage is regulated in a second range of 0.4V to 1.2V.

Abstract: A non-volatile memory device and methods for operating the same are provided. The memory device may have multiple complementary memory cells. The method of blank check includes detecting a state value of each of the true and complementary transistors, generating an upper state value, Wherein a first predetermined amount of the true and complementary transistors have greater state values than the upper state value, generating a lower state value, wherein a second predetermined amount of the true and complementary transistors have less state values than the lower state value, generating a state value range based on a difference between the upper state value and the lower state value, and comparing the state value range to a threshold value to determine whether the plurality of complementary memory cells is in a blank state or a non-blank state. Other embodiments are also disclosed herein.

Abstract: Techniques for suppression of program disturb in flash memory devices are described herein. In an example embodiment, an apparatus comprises a flash memory device coupled to a microprocessor. The flash memory device comprises rows and columns of memory cells, where the memory cells in each row are coupled to a source line and to a select-gate (SG) line, and the memory cells in each column are coupled to a respective bit line (BL). A control circuit in the flash memory device is configured to regulate both a first voltage, of a selected SG line, and a second voltage, of an unselected BL, independently of a power supply voltage of the flash memory device, and to adjust at least one of the first voltage and the second voltage based on a measure of an operating temperature of the flash memory device.

Abstract: Techniques for suppression of program disturb in flash memory devices are described herein. In an example embodiment, an apparatus comprises a flash memory device coupled to a microprocessor. The flash memory device comprises rows and columns of memory cells, where the memory cells in each row are coupled to a source line and to a select-gate (SG) line, and the memory cells in each column are coupled to a respective bit line (BL). A control circuit in the flash memory device is configured to regulate both a first voltage, of a selected SG line, and a second voltage, of an unselected BL, independently of a power supply voltage of the flash memory device, and to adjust at least one of the first voltage and the second voltage based on a measure of an operating temperature of the flash memory device.

Abstract: Techniques for suppression of program disturb in memory devices are described herein. In an example embodiment, a memory device comprises a flash memory array coupled to a control circuit. The flash memory array comprises rows and columns of memory cells, where the memory cells in each row are coupled to a source line and to a select-gate (SG) line, and the memory cells in each column are coupled to a respective bit line (BL). The control circuit is configured to regulate both a first voltage, of a selected SG line, and a second voltage, of an unselected BL, independently of a power supply voltage of the flash memory array, and to adjust at least one of the first voltage and the second voltage based on a measure of an operating temperature of the memory device.

Abstract: A response map descriptively modeling the textual format of a test response of a system verification test is created without a priori understanding of the format of the given response. Such response map is applied to the test response or other similar test responses that share the same format. More specifically, a method of identifying and extracting one or more formats of textual data included in test responses from system verification testing of a system under test is provided, by receiving a first test response including first textual data in one or more formats, generating a response map descriptively modeling the first test response without a priori information of the one or more formats, and applying the response map to a second test response to identify and extract second textual data from the second test response. The second textual data is also in the one or more formats.

Abstract: An electronic device includes a first electrode, a second electrode, and a solid electrolyte made of an ion-conducting material, the first and second electrodes being configured to form a metal dendrite. The device further includes a third electrode, an interface layer contacting the third electrode and a third surface of the electrolyte, the interface layer being an ionic insulator and an electronic insulator. The third electrode and the dendrite are arranged such that the device has two resistive states.

Abstract: An electronic device includes a first electrode, a second electrode, and a solid electrolyte made of an ion-conducting material, the first and second electrodes being configured to form a metal dendrite. The device further includes a third electrode, an interface layer contacting the third electrode and a third surface of the electrolyte, the interface layer being an ionic insulator and an electronic insulator. The third electrode and the dendrite are arranged such that the device has two resistive states.