Patents by Inventor Pawel SZYMANSKI
Pawel SZYMANSKI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230412512Abstract: Systems and methods are disclosed for reducing processing for received redundant data streams. A first network controller receives a first stream of data packets and a second network controller receives a second stream of data packets redundant to the first stream. The first network controller determines, using a value of an identifier of a received packet of the first stream of data packets, that a corresponding packet of the second stream of data packets having the value of the identifier has not already been received. In response to the determining, the first network controller outputs the first data packet. The second network controller determines, using a value of an identifier of a second packet of the second stream of data packets, that the first data packet has already been received and drops the second packet in response to the determining.Type: ApplicationFiled: December 23, 2020Publication date: December 21, 2023Inventors: Tomasz Madajczak, Pawel Szymanski, Raul Diaz
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Publication number: 20230367729Abstract: Generally, this disclosure provides systems, devices, methods and computer readable media for dynamic configuration and enforcement of access lanes to I/O controllers. The System may include a plurality of Input/Output (I/O) controllers and a plurality of lanes. The system may also include a lane mapping module configured to multiplex at least one of the I/O controllers to at least one of the lanes based on a configuration. The system may further include a first processor configured to detect a change request, the change request to modify the configuration from an existing configuration to a new configuration; and a second processor configured to: verify that the new configuration is valid based on a stock keeping unit (SKU) associated with the system; and, if the verification is successful, store the new configuration in non-volatile memory and reset the system.Type: ApplicationFiled: May 18, 2023Publication date: November 16, 2023Inventors: Balaji PARTHASARATHY, Ramamurthy KRITHIVAS, Bradley BURRES, Pawel SZYMANSKI, Yi-Feng LIU
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Patent number: 11693807Abstract: Generally, this disclosure provides systems, devices, methods and computer readable media for dynamic configuration and enforcement of access lanes to I/O controllers. The System may include a plurality of Input/Output (I/O) controllers and a plurality of lanes. The system may also include a lane mapping module configured to multiplex at least one of the I/O controllers to at least one of the lanes based on a configuration. The system may further include a first processor configured to detect a change request, the change request to modify the configuration from an existing configuration to a new configuration; and a second processor configured to: verify that the new configuration is valid based on a stock keeping unit (SKU) associated with the system; and, if the verification is successful, store the new configuration in non-volatile memory and reset the system.Type: GrantFiled: March 19, 2021Date of Patent: July 4, 2023Assignee: Intel CorporationInventors: Balaji Parthasarathy, Ramamurthy Krithivas, Bradley A. Burres, Pawel Szymanski, Yi-Feng Liu
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Publication number: 20220303230Abstract: Examples described herein relate to a network interface device to perform header splitting with payload reordering for one or more packets received at the network interface device and copy headers and/or payloads associated with the one or more packets to at least one memory device.Type: ApplicationFiled: June 2, 2022Publication date: September 22, 2022Inventors: Ping YU, Sarig LIVNE, Qi ZHANG, Xuan DING, Raul DIAZ, Pawel SZYMANSKI
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Publication number: 20210326285Abstract: Generally, this disclosure provides systems, devices, methods and computer readable media for dynamic configuration and enforcement of access lanes to I/O controllers. The System may include a plurality of Input/Output (I/O) controllers and a plurality of lanes. The system may also include a lane mapping module configured to multiplex at least one of the I/O controllers to at least one of the lanes based on a configuration. The system may further include a first processor configured to detect a change request, the change request to modify the configuration from an existing configuration to a new configuration; and a second processor configured to: verify that the new configuration is valid based on a stock keeping unit (SKU) associated with the system; and, if the verification is successful, store the new configuration in non-volatile memory and reset the system.Type: ApplicationFiled: March 19, 2021Publication date: October 21, 2021Inventors: Balaji PARTHASARATHY, Ramamurthy KRITHIVAS, Bradley A. BURRES, Pawel SZYMANSKI, Yi-Feng LIU
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Publication number: 20210288910Abstract: Examples described herein relate to a network interface device and in some examples, the network interface device includes an Ethernet interface, a host interface, circuitry to be configured to copy a packet payload from a host device through the host interface, form a packet based on the packet payload, and transmit the packet through the Ethernet interface, and circuitry to be configured to apply rate limiting and/or traffic shaping for packets received through the Ethernet interface based on hierarchical quality of service (H-QoS).Type: ApplicationFiled: May 27, 2021Publication date: September 16, 2021Inventors: Daniel DALY, Anjali Singhai JAIN, Chih-Jen CHANG, Edmund CHEN, Robert HATHAWAY, Naru Dames SUNDAR, Pawel SZYMANSKI, John MANGAN
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Patent number: 10956351Abstract: Generally, this disclosure provides systems, devices, methods and computer readable media for dynamic configuration and enforcement of access lanes to I/O controllers. The System may include a plurality of Input/Output (I/O) controllers and a plurality of lanes. The system may also include a lane mapping module configured to multiplex at least one of the I/O controllers to at least one of the lanes based on a configuration. The system may further include a first processor configured to detect a change request, the change request to modify the configuration from an existing configuration to a new configuration; and a second processor configured to: verify that the new configuration is valid based on a stock keeping unit (SKU) associated with the system; and, if the verification is successful, store the new configuration in non-volatile memory and reset the system.Type: GrantFiled: September 10, 2019Date of Patent: March 23, 2021Assignee: Intel CorporationInventors: Balaji Parthasarathy, Ramamurthy Krithivas, Bradley Burres, Pawel Szymanski, Yi-Feng Liu
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Publication number: 20200004713Abstract: Generally, this disclosure provides systems, devices, methods and computer readable media for dynamic configuration and enforcement of access lanes to I/O controllers. The System may include a plurality of Input/Output (I/O) controllers and a plurality of lanes. The system may also include a lane mapping module configured to multiplex at least one of the I/O controllers to at least one of the lanes based on a configuration. The system may further include a first processor configured to detect a change request, the change request to modify the configuration from an existing configuration to a new configuration; and a second processor configured to: verify that the new configuration is valid based on a stock keeping unit (SKU) associated with the system; and, if the verification is successful, store the new configuration in non-volatile memory and reset the system.Type: ApplicationFiled: September 10, 2019Publication date: January 2, 2020Applicant: Intel CorporationInventors: BALAJI PARTHASARATHY, RAMAMURTHY KRITHIVAS, BRADLEY BURRES, PAWEL SZYMANSKI, Yi-Feng LIU
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Patent number: 10242197Abstract: A data processing system (DPS) provides protection for firmware. The DPS comprises (a) a host module comprising a management engine and (b) a security module in communication with the host module. The security module comprises a security coprocessor and a secret identifier for the security module. The DPS also comprises at least one machine-accessible medium comprising host firmware and security firmware. The host firmware, when executed by the management engine, enables to management engine to determine whether the security module is in communication with the host module, based on the secret identifier for the security module. The security firmware, when executed by the security coprocessor, enables the security coprocessor (a) to verify integrity of the host firmware and (b) to prevent the host module from booting with the host firmware in response to a determination that the host firmware has lost integrity. Other embodiments are described and claimed.Type: GrantFiled: September 23, 2016Date of Patent: March 26, 2019Assignee: Intel CorporationInventors: Justyna Zander, Marek Zmuda, Igor A. Tatourian, Pawel Szymanski
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Publication number: 20180285562Abstract: Technology for a computing system is described. The computing system can include memory, a controller, and a security management module. The controller can receive a block erase command for erasing data stored in a block of memory. The controller can store information associated with the block erase command in a store, wherein the information includes a block address associated with the data to be erased based on the block erase command. The security management module can read block addresses from the store, update a block erase count array over a defined interval to include block addresses read from the store, compare the block erase count array to a defined threshold, identify block addresses for which the block erase count array is above the defined threshold, and deny subsequent block erase commands for the identified block addresses.Type: ApplicationFiled: March 31, 2017Publication date: October 4, 2018Applicant: Intel CorporationInventors: Sivakumar Radhakrishnan, Mahesh S. Natu, Pawel Szymanski, Zhenyu Zhu, Malay Trivedi, Kirk D. Brannock, Geoffrey S. Strongin
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Patent number: 10073742Abstract: Technologies for providing manageability redundancy for micro server and clustered System-on-a-Chip (SoC) deployments are presented. A configurable multi-processor apparatus may include multiple integrated circuit (IC) blocks where each IC block includes a task block to perform one or more assignable task functions and a management block to perform management functions with respect to the corresponding IC block. Each task block and each management block may include one or more instruction processors and corresponding memory. Each IC block may be controllable to perform a function of one or more other IC blocks. The IC blocks may communicate with each other via a management communication infrastructure that may include a communication path from each of the management blocks to each of the other management blocks. Via the management communication infrastructure, the management blocks may bridge communication paths between pairs of management blocks.Type: GrantFiled: June 9, 2016Date of Patent: September 11, 2018Assignee: Intel CorporationInventors: Robert C. Swanson, Mariusz Oriol, Janusz Jurski, Piotr Sawicki, Robert W. Cone, William J. O'Sullivan, Mariusz Stepka, Babak Nikjou, Madhusudhan Rangarajan, Pawel Szymanski, Piotr Kwidzinski, Robert Bahnsen, Mallik Bulusu
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Publication number: 20180089435Abstract: A data processing system (DPS) provides protection for firmware. The DPS comprises (a) a host module comprising a management engine and (b) a security module in communication with the host module. The security module comprises a security coprocessor and a secret identifier for the security module. The DPS also comprises at least one machine-accessible medium comprising host firmware and security firmware. The host firmware, when executed by the management engine, enables to management engine to determine whether the security module is in communication with the host module, based on the secret identifier for the security module. The security firmware, when executed by the security coprocessor, enables the security coprocessor (a) to verify integrity of the host firmware and (b) to prevent the host module from booting with the host firmware in response to a determination that the host firmware has lost integrity. Other embodiments are described and claimed.Type: ApplicationFiled: September 23, 2016Publication date: March 29, 2018Applicant: lntel CorporationInventors: JUSTYNA ZANDER, MAREK ZMUDA, IGOR A. TATOURIAN, PAWEL SZYMANSKI
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Publication number: 20180081847Abstract: Generally, this disclosure provides systems, devices, methods and computer readable media for dynamic configuration and enforcement of access lanes to I/O controllers. The System may include a plurality of Input/Output (I/O) controllers and a plurality of lanes. The system may also include a lane mapping module configured to multiplex at least one of the I/O controllers to at least one of the lanes based on a configuration. The system may further include a first processor configured to detect a change request, the change request to modify the configuration from an existing configuration to a new configuration; and a second processor configured to: verify that the new configuration is valid based on a stock keeping unit (SKU) associated with the system; and, if the verification is successful, store the new configuration in non-volatile memory and reset the system.Type: ApplicationFiled: March 27, 2015Publication date: March 22, 2018Applicant: Intel CorporationInventors: BALAJI PARTHASARATHY, RAMAMURTHY KRITHIVAS, BRADLEY BURRES, PAWEL SZYMANSKI, Yi-Feng LIU
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Patent number: 9547497Abstract: Technologies for facilitating inter-system-on-a-chip (SoC) communication include a first SoC, a second SoC, and a dedicated manageability controller network. The first SoC includes a first main processor, a first manageability controller, and a memory dedicated to the first manageability controller and having manageability controller firmware stored thereon. The first manageability controller is different from the first main processor and to control functions of the first SoC. The second SoC is different from the first SoC and includes a second main processor and a second manageability control, which is different from the second main processor and to control functions of the second SoC. The second SoC is to access the manageability controller firmware of the memory of the first SoC over the dedicated manageability network.Type: GrantFiled: September 27, 2013Date of Patent: January 17, 2017Assignee: Intel CorporationInventors: Robert C. Swanson, Robert W. Cone, William J. O'Sullivan, Mariusz Oriol, Pawel Szymanski, Babak Nikjou, Madhusudhan Rangarajan, Janusz Jurski, Piotr Kwidzinski, Mariusz Stepka, Piotr Sawicki
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Publication number: 20160292038Abstract: Technologies for providing manageability redundancy for micro server and clustered System-on-a-Chip (SoC) deployments are presented. A configurable multi-processor apparatus may include multiple integrated circuit (IC) blocks where each IC block includes a task block to perform one or more assignable task functions and a management block to perform management functions with respect to the corresponding IC block. Each task block and each management block may include one or more instruction processors and corresponding memory. Each IC block may be controllable to perform a function of one or more other IC blocks. The IC blocks may communicate with each other via a management communication infrastructure that may include a communication path from each of the management blocks to each of the other management blocks. Via the management communication infrastructure, the management blocks may bridge communication paths between pairs of management blocks.Type: ApplicationFiled: June 9, 2016Publication date: October 6, 2016Inventors: Robert C. Swanson, Mariusz Oriol, Janusz Jurski, Piotr Sawicki, Robert W. Cone, William J. O'Sullivan, Mariusz Stepka, Babak Nikjou, Madhusudhan Rangarajan, Pawel Szymanski, Piotr Kwidzinski, Robert Bahnsen, Mallik Bulusu
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Publication number: 20160202994Abstract: Technologies for facilitating inter-system-on-a-chip (SoC) communication include a first SoC, a second SoC, and a dedicated manageability controller network. The first SoC includes a first main processor, a first manageability controller, and a memory dedicated to the first manageability controller and having manageability controller firmware stored thereon. The first manageability controller is different from the first main processor and to control functions of the first SoC. The second SoC is different from the first SoC and includes a second main processor and a second manageability control, which is different from the second main processor and to control functions of the second SoC. The second SoC is to access the manageability controller firmware of the memory of the first SoC over the dedicated manageability network.Type: ApplicationFiled: September 27, 2013Publication date: July 14, 2016Inventors: Robert C. SWANSON, Robert W. CONE, William J. O'SULLIVAN, Mariusz ORIOL, Pawel SZYMANSKI, BABAK NIKJOU, Madhusudhan RANGARAJAN, Janusz JURSKI, Piotr KWIDZINSKI, Mariusz STEPKA, Piotr SAWICKI
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Patent number: 9367406Abstract: Technologies for providing manageability redundancy for micro server and clustered System-on-a-Chip (SoC) deployments are presented. A configurable multi-processor apparatus may include multiple integrated circuit (IC) blocks where each IC block includes a task block to perform one or more assignable task functions and a management block to perform management functions with respect to the corresponding IC block. Each task block and each management block may include one or more instruction processors and corresponding memory. Each IC block may be controllable to perform a function of one or more other IC blocks. The IC blocks may communicate with each other via a management communication infrastructure that may include a communication path from each of the management blocks to each of the other management blocks. Via the management communication infrastructure, the management blocks may bridge communication paths between pairs of management blocks.Type: GrantFiled: August 14, 2013Date of Patent: June 14, 2016Assignee: Intel CorporationInventors: Robert C. Swanson, Mariusz Oriol, Janusz Jurski, Piotr Sawicki, Robert W. Cone, William J. O'Sullivan, Mariusz Stepka, Babak Nikjou, Madhusudhan Rangarajan, Pawel Szymanski, Piotr Kwidzinski, Robert Bahnsen, Mallik Bulusu
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Publication number: 20150052389Abstract: Technologies for providing manageability redundancy for micro server and clustered System-on-a-Chip (SoC) deployments are presented. A configurable multi-processor apparatus may include multiple integrated circuit (IC) blocks where each IC block includes a task block to perform one or more assignable task functions and a management block to perform management functions with respect to the corresponding IC block. Each task block and each management block may include one or more instruction processors and corresponding memory. Each IC block may be controllable to perform a function of one or more other IC blocks. The IC blocks may communicate with each other via a management communication infrastructure that may include a communication path from each of the management blocks to each of the other management blocks. Via the management communication infrastructure, the management blocks may bridge communication paths between pairs of management blocks.Type: ApplicationFiled: August 14, 2013Publication date: February 19, 2015Inventors: Robert C. Swanson, Mariusz Oriol, Janusz Jurski, Piotr Sawicki, Robert W. Cone, William J. O'Sullivan, Mariusz Stepka, Babak Nikjou, Madhusudhan Rangarajan, Pawel Szymanski, Piotr Kwidzinski, Robert Bahnsen, Mallik Bulusu
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Publication number: 20090003959Abstract: An anchor bolt comprising a main body (4), a bolt head (5), at least one supporting blade (6), an internal thread (2); and an external thread (3); wherein the external thread (3) is disposed along the external surface of the main body (4); the internal thread (2) is disposed along the internal surface of the main body (4) and/or the bolt head (5); and the supporting blade is attached to the main body and the bolt head (5).Type: ApplicationFiled: June 27, 2008Publication date: January 1, 2009Applicant: FLOWAIR Glogowski i Brzezinski sp.j.Inventors: Maciej GLOGOWSKI, Sebastian KRZESZOWSKI, Pawel SZYMANSKI