Abstract: A computer system and associated methods are disclosed for mitigating side-channel attacks using memory page remapping. The computer system includes a main memory and a shared cache, the shared cache implementing cache set associativity determined by a portion of memory addresses of the main memory. Multiple physical memory pages are reserved for mapping to a virtual memory page, the physical memory pages differing in the respective portions of their memory addresses determining cache set associativity. Accesses to the virtual memory page result in a mapping of one of the reserved physical memory pages to the virtual memory page, with remapping events causing different ones of the physical memory pages to become mapped. This remapping results in varying cache set associativity of elements stored in the virtual memory page over time.

Abstract: A computer system and associated methods are disclosed for mitigating side-channel attacks using a shared cache. The computer system includes a host having a main memory and a shared cache. The host executes a virtual machine manager (VMM) that determines respective security keys for a plurality of co-located virtual machines (VMs). A cache controller for the shared cache includes a scrambling function that scrambles addresses of memory accesses performed by threads of the VMs according to the respective security keys. Different cache tiers may implement different scrambling functions optimized to the architecture of each cache tier. Security keys may be periodically updated to further reduce predictability of shared cache to memory address mappings.

Abstract: A computer system and associated methods are disclosed for mitigating side-channel attacks using a shared cache. The computer system includes a main memory, a shared cache and a cache controller for the shared cache including a scrambling function that scrambles addresses of memory accesses according to the respective scrambling keys selected for a sequence of time periods. Different cache tiers may implement different scrambling functions optimized to the architecture of each cache tier. Scrambling keys may be updated to reduce predictability of shared cache to memory address mappings. These updates may occur opportunistically, on demand or on specified schedule. Multiple scrambling keys may be simultaneously active during transitions between active time periods.