Abstract: Provided herein is a non-uniform multi-stage distributed circuit capable of operation with an improved gain-bandwidth product. The circuit can include an input port, an output port and a transmission line coupled therebetween. Two or more amplifier stages can be coupled successively to the transmission line. Each amplifier stage can include a transistor having a transistor parameter, which can be scaled to be less than the transistor parameter of any preceding amplifier stage. The inductance of each portion of the transmission line between adjacent stages can also be scaled to be less than the inductance of the portion of the transmission line between any preceding amplifier stages. The inductance can be scaled in addition to or instead of the transistor parameter.

Abstract: Provided herein is a non-uniform multi-stage distributed circuit capable of operation with an improved gain-bandwidth product. The circuit can include an input port, an output port and a transmission line coupled therebetween. Two or more amplifier stages can be coupled successively to the transmission line. Each amplifier stage can include a transistor having a transistor parameter, which can be scaled to be less than the transistor parameter of any preceding amplifier stage. The inductance of each portion of the transmission line between adjacent stages can also be scaled to be less than the inductance of the portion of the transmission line between any preceding amplifier stages. The inductance can be scaled in addition to or instead of the transistor parameter.

Abstract: A clock and data recovery system using a distributed variable delay line is provided. The clock and data recovery system can use a delay-locked loop methodology to align a local clock with an incoming data stream. The variable delay line can include a transmission line coupled with a plurality of variable capacitors responsive to a control voltage. The variable delay line can also have a ladder configuration of multiple LC subcircuits each having a variable impedance responsive to a control voltage.

Abstract: A clock and data recovery system using a distributed variable delay line is provided. The clock and data recovery system can use a delay-locked loop methodology to align a local clock with an incoming data stream. The variable delay line can include a transmission line coupled with a plurality of variable capacitors responsive to a control voltage. The variable delay line can also have a ladder configuration of multiple LC subcircuits each having a variable impedance responsive to a control voltage.

Abstract: A wideband distributed mixer capable of operation over a wide range of frequencies is provided. The mixer can include a plurality of N mixer stages and monolithic transmission lines integrated together on a common semiconductor substrate. The length of each transmission line between adjacent stages can be predetermined such that an IF signal output from each stage is in-phase with the IF signal output from any preceding stage, allowing the mixer to output a mixed IF signal that is a constructive sum of the IF output signals from each constituent stage. The number of mixer stages as well as the design architectures and topologies for each stage can be varied according to the needs of the application.

Abstract: A clock and data recovery system using a distributed variable delay line is provided. The clock and data recovery system can use a delay-locked loop methodology to align a local clock with an incoming data stream. The variable delay line can include a transmission line coupled with a plurality of variable capacitors responsive to a control voltage. The variable delay line can also have a ladder configuration of multiple LC subcircuits each having a variable impedance responsive to a control voltage.