Abstract: The subject invention is a system, apparatus and/or method of forming interconnects on a semiconductor wafer. Particularly, the subject invention provides interconnect routing using parallel lines on a semiconductor wafer. The method includes producing a plurality of spaced, parallel interconnects on a wafer, and producing interruptions in selective ones of the plurality of interconnects where the connection should be disrupted. Preferably, the plurality of spaced, parallel lines are formed over the entire die region of the wafer and are spaced from one another by a predetermined width. In one form, a mask having a plurality of spaced, parallel lines may be used.